Revision History

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)
Document ID
DS956
Release Date
2025-01-13
Revision
1.14 English

The following table shows the revision history for this document.

Section Revision Summary
1/13/2025 Version 1.14
General Added VM2152 devices throughout. Updated Table 1 including production release of the XCVM2152 with speed grades -2MSE, -2MSI, -2MLE, -2MLI, -1MSE, -1MSI, and -1MLI (VCCINT = 0.80V) using the Vivado Design Suite 2024.2.1 v2.01.

This includes updates to the following tables:
Integrated High-speed Channelized Cryptography Engine Added this table for the VM2152 devices only.
9/20/2024 Version 1.13
General updates

Updated Table 1 including production release of the XQVM1102 with speed grades -2MSI, -1MSM, -1MSI (VCCINT = 0.80V) and -1LSI (VCCINT = 0.70V) using the Vivado Design Suite 2024.1.2 v2.03.

This includes updates to the following tables:
Video Decoder Engines Performance Removed table because no Versal Prime devices support this feature.
7/24/2024 Version 1.12
General updates

Updated Table 1 including production release of the XCVM2202 with speed grade -2HSI (VCCINT = 0.88V) using the Vivado Design Suite 2024.1 v2.01.

This includes updates to the following tables:
Absolute Maximum Ratings Increased the maximum storage temperature to 150°C.
Table 2 Removed redundant Notes 1 and 2.
Clocks and Reset Added FCPM5_TOPSW_CLK to Table 5 and Note 13.
Accelerator RAM Switching Characteristics Corrected the -2L/-1L from 0.80V to 0.70V for VCC_PSLP see the Available Speed Grades and Operating Voltages table.
GTM Transceiver Switching Characteristics Removed the 58 Gb/s condition in the following tables:
Programmable Logic Integrated Block for PCIe Added a note to each table in this section to clarify that the specifications are only for the integrated blocks forPCIe.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) Added a note to each table in this section to clarify that the specifications are only for the integrated blocks forPCIe.
4/30/2024 Version 1.11
General updates

Updated Table 1 including production release of the XCVM2202 with speed grade -2HSI (VCCINT = 0.88V) using the Vivado Design Suite 2023.2.2 v2.01.

This includes updates to the following tables:
Absolute Maximum Ratings Added VCCINT_GT specification.
Recommended Operating Conditions Updated VGTYP_AVCC and VGTYM_AVCC with voltages based upon temperature ranges (E, I, Q, or M).
Available Speed Grades and Operating Voltages Updated Note 5.
Power Supply Requirements Added reference links.
Device Identification Updated IDCODE for XCVM1102.
DDR4 and LPDDR4/4X Memory Interface Controller Updated Note 5.
GTM Transceiver DC Input and Output Levels Revised VDIFF maximum from 800 mV to 1600 mV.
GTY and GTYP Transceiver DC Input and Output Levels Revised VDIFF maximum from 800 mV to 1600 mV.
GTY and GTYP Transceiver Reference Clock Oscillator Selection Phase Noise Mask Interchanged symbols LCPLL and RINGPLL.
2/29/2024 Version 1.10
General updates

Updated Table 1 including production release:

  • XCVM1102 with speed grades -2HSI and -2LLI using the Vivado Design Suite 2024.1 v2.01.
  • XCVM2202 with speed grade -2LLI using the Vivado Design Suite 2024.1 v2.02.

This could include updates to the following tables:
Absolute Maximum Ratings Revised the transceiver REFCLK_AC maximum input voltage from 1.200V to 1.350V.
Block RAM Switching Characteristics TRCKO_DO and TRCKO_DO_REG values changed for -2LLI.
DDR4 and LPDDR4/4X Memory Interface Controller Removed the LPDDR4/4X pin efficient component interface limitation.
Table 2 Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV.
GTM Transceiver Performance Updated to support all the AMD Versal™ Prime devices, added -2H specifications to Table 1 and Table 1.
GTM Transceiver PLL/Lock Time Adaptation Update the TDLOCK values for GTM PAM4.
Table 2 Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV.
GTY and GTYP Transceiver Performance Updated Table 1 and Table 1 to remove the -3H speed files to match the Versal Prime devices offered.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated the GTY transceiver -2H values.
11/08/2023 Version 1.9
General updates Updated Table 1 including:
  • Production release of the XCVM1302 and XCVM1402 with speed grade -2LLI using the Vivado Design Suite 2023.2 v2.03.
  • Production release of the XCVM1502 with speed grade -2LLI using the Vivado Design Suite 2023.2 v2.04.
  • Added the XCVM2202.

Includes updates to Speed Grade Designations, Production Silicon and Software Status, Device Pin-to-Pin Output Parameter Guidelines, Device Pin-to-Pin Input Parameter Guidelines, and Package Parameter Guidelines.
Recommended Operating Conditions Updated Note 9 with PSIO operation information. Updated Note 10.
Available Speed Grades and Operating Voltages Updated Note 4.
DDR4 and LPDDR4/4X Memory Interface Controller Clarified the values for LPDDR4/4X XPIO bank performance.
GTM Transceiver Performance Removed notes from FGTMPAM42MAX and FGTMPAM44MAX because they do not apply for the data rates listed.
GTM Transceiver Reference Clock Switching Characteristics Added Note 1.
GTM Transceiver Digital Monitor Clock Added table.
GTY and GTYP Transceiver Reference Clock Switching Characteristics Added Note 1.
GTY and GTYP Transceiver Digital Monitor Clock Added table.
9/08/2023 Version 1.8
General updates Updated the Table 1 including:
  • Production release of the XCVM2302 and XCVM2902 with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.1 v2.00
  • Production release of the XCVM2302 and XCVM2902 with speed grades -3HSE, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI, using the Vivado Design Suite 2023.1.1 v2.01
  • Production release of the XCVM2502 with speed grades -3HSE, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, -1MLI, -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.1.2 v2.01
  • Production release of the XQVM1502 with speed grades -2MSI, -1MSM, -1MSI, and -1LSI using the Vivado Design Suite 2023.1.1 v2.03

Includes updates to Speed Grade Designations, Production Silicon and Software Status, Device Pin-to-Pin Output Parameter Guidelines, Device Pin-to-Pin Input Parameter Guidelines, and Package Parameter Guidelines.
GTY and GTYP Transceiver Electrical Compliance Clarified PCIe support for GTYP transceivers.
6/07/2023 Version 1.7
General updates Updated the Table 1 including:
  • Production release of the XCVM2302 and XCVM2902 with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.1 v2.00

Includes updates to Speed Grade Designations, Production Silicon and Software Status, Device Pin-to-Pin Output Parameter Guidelines, Device Pin-to-Pin Input Parameter Guidelines, and Package Parameter Guidelines.
Summary Clarified that the I and M temperature grades are also supported by the Versal Prime devices.
Recommended Operating Conditions Updated Tj to add military (M) temperature specifications.
DC Characteristics Over Recommended Operating Conditions Added IL specifications.
VIN Maximum Allowed AC Voltage Overshoot and Undershoot Added Note 3 and Note 4 for -1MSM devices.
Table 4 Added Notes 1, 2, and 3.
Table 5 Added Notes 2, 4, 6, 8, 10, and 12.
PS Gigabit Ethernet MAC Controller Interface Added Note 2 to FGEMTSUREFCLK.
GTM Transceiver DC Input and Output Levels Added VCMOUTDC to Table 1. Updated the DVPPOUT output swing setting to 1000100.
GTY and GTYP Transceiver DC Input and Output Levels Removed the row for VCMOUTDC when remote RX is terminated to GND and added Note 2. Updated Note 3.
3/28/2023 Version 1.6
General updates Updated the Table 1 including:
  • Production release of the XCVM1502 with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2022.2 v2.00
  • Production release of the XCVM1502 with speed grades -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI using the Vivado Design Suite 2022.2.1 v2.01
  • Production release of the XCVM1502 with speed grades -2HSI using the Vivado Design Suite 2022.2.2 v2.02
  • Production release of the XQVM1402 with speed grades -2MSI, -1MSI, -1MSM, and -1LSI using the Vivado Design Suite 2022.2.1 v2.02
  • Production release of the XCVM1802 device in the -2LLI speed grade using the Vivado Design Suite 2022.2.1 v2.11.

Includes updates toSpeed Grade Designations, Production Silicon and Software Status, Device Pin-to-Pin Output Parameter Guidelines, Device Pin-to-Pin Input Parameter Guidelines, and Package Parameter Guidelines.
Absolute Maximum Ratings Revised the IDCIN_GTM_AVTT and IDCIN_GTM_GND values from 12 mA to 16 mA.
Recommended Operating Conditions Updated VCCINT with values for -2LLI devices and added Note 7.
Available Speed Grades and Operating Voltages Updated -2LLI device code and added Note 5.
Updated VCC_CPM5 values because devices with CPM5 do not support the -2HSI or -2LLI speed grades.
Updated Notes 1, 2, and 3.
Power Supply Requirements Updated description to add references to the PDM tool.
Speed Grade Designations Removed -2MLI, -2LLI, -1MLI, and -1LLI speed grades from the XQVM1102, XQVM1402, and XQVM1502.
Production Silicon and Software Status Added Note 5 to Production Silicon and Software Status
Added N/A to the columns for XQ devices that do not support low static-power grades.
Device Identification Revised the VM1102 and VM1502 IDCODEs and added XQVM1402, XCVM2202, and XCVM2302 IDCODEs.
Processing System Performance Characteristics Updated notes in Table 1 and Table 2.
PMC JTAG and SelectMAP Updated Note 1 in Table 1.
PMC Quad-SPI Controller Interface Updated the FQSPI_REFCLK maximum for Quad-SPI device clock frequency operating at ≤37.5 MHz (Loopback disabled) from 150 MHz to 300 MHz.
Block RAM Switching Characteristics To further delineate the specifications for block RAM clock-to-out delays, added a column for -2LLI and renamed -2L column to -2LSE, -2LLE.
Device Pin-to-Pin Output Parameter Guidelines Added column for -2LLI and renamed column to -2LSE, -2LLE. Added XCVM2302 and XCVM2902 values.
Device Pin-to-Pin Input Parameter Guidelines Added column for -2LLI and renamed column to -2LSE, -2LLE. Added XCVM2302 and XCVM2902 values.
Package Parameter Guidelines Updated XQVM1102, added XQVM1502, XCVM2302 and XCVM2902 values.
GTM Transceiver DC Input and Output Levels Updated the DVPPIN PAM4 maximum specification in Table 1. Added Table 3.
GTM Transceiver Performance Added notes to the output divider column for both measured BER and availability of certain data rates.
GTM Transceiver PLL/Lock Time Adaptation Updated conditions for TLOCK.
GTM Transceiver Transmitter and Receiver Switching Characteristics Removed the PAM4 82.5 Gb/s sinusoidal jitter condition.
Table 2 Updated RXPPMTOL conditions and Note 2, and added Note 1.
GTY and GTYP Transceiver DC Input and Output Levels Revised VCMOUTDC and VCMOUTAC equations in GTY and GTYP Transceiver DC Input and Output Levels.
Updated VOL, VOH, and VCMOUT minimum/maximum values in Table 3.
GTY and GTYP Transceiver Performance In Table 2, revised the GTYP maximum line rate and the LCPLL line rate range.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated FTXIN and FRXIN values for some data width conditions.
8/02/2022 Version 1.5
General updates Updated the Table 1 including production release of some of the devices/speed grade/operating voltages using the Vivado Design Suite 2022.1.1 v2.10 in Speed Grade Designations and Production Silicon and Software Status.
Speed Grade Designations Moved the -2LLI (VCCINT = 0.70V) speed file to Evaluation in some devices where it was listed as production. This speed file is not available in the software tools.
DC Characteristics Over Recommended Operating Conditions Updated the ICC_BATT conditions and values.
PMC SD/SDIO Controller Interface Added TSDDCK and TSDCKD minimum values and updated the TSDSDR12DCK minimum value.
PMC eMMC Controller Interface Added TEMMEDCK and TEMMCCKD minimum values.
Device Pin-to-Pin Output Parameter Guidelines Updated the XCVM1502 values and added the -2H values for XCVM1302, XCVM1402, and XCVM1802.
Device Pin-to-Pin Input Parameter Guidelines Updated the XCVM1502 values and added the -2H values for XCVM1302, XCVM1402, and XCVM1802.
GTM Transceiver User Clock Switching Characteristics Updated table values to match the maximum 58 Gb/s line rate.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) Clarified that Overdrive support is not available on -1L (0.70V) devices in Table 4, Table 5, and Table 6.
5/02/2022 Version 1.4
General updates Added XQ devices: XQVM1102, XQVM1402, XQVM1502, and XQVM1802.
Absolute Maximum Ratings Revised the VGTY_AVCC maximums from 0.97V to 1.01V. Revised the GT transceivers VIN specifications and added unpowered and powered values for VIN_DC and VIN_AC. Revised the transceiver reference clock absolute input AC and DC voltages. Removed duplicate IDCIN-FLOAT rating and note. Removed note 9.
Available Speed Grades and Operating Voltages Added the -1MSM speed grade for XQ devices (-1MP-m-S device code).
Power Supply Requirements Updated the description.
AC Switching Characteristics Updated the Table 1 including production release of some of the devices/speed grade/operating voltages using the Vivado Design Suite 2022.1 v2.06 in Speed Grade Designations and Production Silicon and Software Status.
Clocks and Reset Added note 2 to Table 1.
PMC Octal-SPI Controller Interface Added values to Table 1 and updated note 1.
PMC SD/SDIO Controller Interface Added values to Table 1 and updated note 1.
PMC eMMC Controller Interface Added values and notes 3 and 4 to Table 1 and updated note 1.
DDR4 and LPDDR4/4X Memory Interface Controller Added note 7 to Table 1
GTM Transceiver Specifications Added GTM transceiver specifications. Some Versal Prime devices have GTM transceivers, see the Versal Architecture and Product Data Sheet: Overview (DS950).
GTY and GTYP Transceiver Performance Added the -2H column. Some XC devices offer a -2HSI device and others offer a -3SE device. See the Speed and Temperature Grade table in the Versal Architecture and Product Data Sheet: Overview (DS950).
Programmable Logic Integrated Block for PCIe Updated Table 2.
1/06/2022 Version 1.3
Summary and General Updates Added the XCVM2202, XCVM2302, and removed XCVM2602 devices.
Added the GTM transceiver, PCIe 5.0, and CPM5 specifications where applicable.
Absolute Maximum Ratings Revised the maximum VCCO from 3.465V to 3.63V for certain HDIO and PSIO banks.
Added VREF specifications.
Removed TSOL guidelines. See Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for appropriate specifications by package type.
DC Characteristics Over Recommended Operating Conditions Updated the HDIO, PSIO, and XPIO maximum capacitance and added Note 2.
Available Speed Grades and Operating Voltages Added the Vivado Design Tools Device Code column.
AC Switching Characteristics Updated to Vivado Design Suite 2021.2.1 v2.05 for XCVM1802 and v1.02 for XCVM1302, XCVM1402.
Added the Evaluation Product Specification description.
Speed Grade Designations Revised the available speed specifications by device.
Production Silicon and Software Status Revised the production released version of the XCVM1802 to Vivado Design Suite 2021.2.1 v2.05 and added Note 4.
PS USB Controller Interface Revised TULPICKD input hold time from 0 to 0.5 ns (500 ps).
Table 6 Added Note 4 limiting the RLDRAM3 maximum performance for -2L and -1L speed grades.
Device Pin-to-Pin Output Parameter Guidelines Revised the XCVM1802 speed specification values for Vivado Design Suite 2021.2.1 v2.05 and added the Vivado Design Suite 2021.2.1 v1.02 values for XCVM1302 and XCVM1402.
Device Pin-to-Pin Input Parameter Guidelines Revised the XCVM1802 speed specification values for Vivado Design Suite 2021.2.1 v2.05 and added the Vivado Design Suite 2021.2.1 v1.02 values for XCVM1302 and XCVM1402.
Package Parameter Guidelines Added some XCVM1302 and XCVM1402 values.
7/01/2021 Version 1.2
Recommended Operating Conditions Added Note 10.
AC Switching Characteristics Updated the speed file versions to Vivado Design Suite 2021.1 v2.01.
Speed Grade Designations Moved the XCVM1802 to production for the following speed grades:
  • -2MSE, -2MLE, -2MSI, -2MLI (VCCINT = 0.80V)
  • -1MSE, -1MLE, -1MSI, -1MLI (VCCINT = 0.80V)
Production Silicon and Software Status Updated the software status for the following speed grades to Vivado Design Suite 2021.1 v2.01.
  • -2MSE, -2MLE, -2MSI, -2MLI (VCCINT = 0.80V)
  • -1MSE, -1MLE, -1MSI, -1MLI (VCCINT = 0.80V)
Processing System Performance Characteristics In Table 1, updated FRPUMAX for the -3/-2 (0.88V (H)) speed grades.
Added FPLATB_CLK to Table 2.
PS CAN FD Controller Interface Added Note 2.
PS Trace Interface Updated Note 2 and added Note 4.
Programmable Logic Performance Characteristics Updated Table 3 for -2/-1 (0.80V (M) and 0.70V (L)) speed grades.
In Table 6:
  • Removed Note 4: Maximum performance for interfaces using more than one bank.
  • Added Note 1.
  • Revised the -1 performance values for DRAM type DDR4 single rank component.
  • Revised the -1M performance value for DRAM type 1 rank RDIMM, DIMM.
Accelerator RAM Switching Characteristics Added the section because the accelerator RAM is available in the VM1102 device.
Device Pin-to-Pin Output Parameter Guidelines Updated the TICKOFMMCM values to the speed specifications in Vivado Design Suite 2021.1.
Device Pin-to-Pin Input Parameter Guidelines Updated the setup and hold values to the speed specifications in Vivado Design Suite 2021.1.
DDR4 and LPDDR4/4X Memory Interface Controller Added Note 1 to Table 1, and updated Note 5.
GTY and GTYP Transceiver Configuration Interface Port Switching Characteristics Reduced the maximum GTYAPB3CLK frequency in Table 1.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated values in Table 2.
4/14/2021 Version 1.1
General updates Added GTYP transceiver specifications.
Summary Added VCC_PMC overdrive support.
Table 1 Updated the notes.
Table 1 Revised maximum VCCBATT, added minimum CFU reference clock frequency to FCFU_REFCLK, added overdrive conditions to VCC_PMC , added Notes 2, 3, 4, 9, 13, and updated Note 16.
Available Speed Grades and Operating Voltages Updated table with standard and overdrive modes. Added Note 4.
Table 1 Added table.
VIN Maximum Allowed AC Voltage Overshoot and Undershoot Added note 3 to Table 2.
Table 3 Updated VIL maximum and VIH minimum for LVSTL06_12 and LVSTL_11.
Table 8 Removed LVSTL_11 (VOH = 33). Added Note 2.
Table 9 Removed LVSTL_11 (VOH = 33).
LVDS DC Specifications (LVDS15) Added VICM_AC and Note 5.
AC Switching Characteristics Updated the speed file versions and the definitions for engineering sample, pre-production, and production product specification.
Speed Grade Designations Moved the XCVM1802 to production for the following speed grades:
  • -2LSE, -2LLE (VCCINT = 0.70V)
  • -1LSE, -1LLE, -1LSI, -1LLI (VCCINT = 0.70V)
Production Silicon and Software Status The XCVM1802 is production released using Vivado Design Suite 2020.3 v2.00.
Device Identification Updated the IDCODE for the XCVM1802, and added notes to explain the table fields.
Processing System Performance Characteristics Updated Table 1.
Added FPSFCIDMA_CLK and Note 1 to Table 2.
Clocks and Reset Added TMODEPOR, and TPORMODE to Table 3.
Added FFPD_LSBUS_CLK and Note 4 to Table 4.
Added FRPLL_TO_XPD_CLK, FLPD_LSBUS_CLK, FTS_REFCLK, FPSM_REFCLK, FDBG_LPD_CLK, FUSB_REFCLK, FDBG_TS_CLK, and Notes 1, 5, 7, and 11 to Table 5.
In Table 6, updated the IRO tolerance range.
In Table 7, added FEFUSE_REFCLK, FSMON_REFCLK, FNPI_REFCLK, FPPLL_TO_XPD_CLK, FNPLL_TO_XPD_CLK, FLSBUS_REFCLK, FAXI_TO_REFCLK, FUSB_SREFCLK, and FHSM0_REFCLK. Revised the -3 specifications for FPL0_REFCLK, FPL1_REFCLK, FPL2_REFCLK, and FPL3_REFCLK. Updated the Notes 1 and 4.
Added Note 1 to Table 8.
PMC JTAG and SelectMAP Extensive updates to Table 1 and Table 2.
PMC Quad-SPI Controller Interface Extensive changes to the table. Updated Note 1 and added Note 2 and 5.
PMC Octal-SPI Controller Interface Removed load condition column. Updated Note 1.
PS USB Controller Interface Added TULPIDCK, TULPICKD, and TULPICKO.
PS Gigabit Ethernet MAC Controller Interface Added FGEMTSUREFCLK.
PS Trace Interface Updated FTCECLK and Note 3.
Network on Chip Switching Characteristics Updated the performance values in the table.
Programmable Logic Performance Characteristics Updated values in Table 1. Updated values in Table 2 and added Notes 3 and 4. Updated the values in Table 3. Updated the values in Table 6 and added Note 4: Maximum performance for interfaces using more than one bank. Removed the LVDS Native-Mode 1000BASE-X Support table.
Block RAM Switching Characteristics Updated TRCKO_DO and TRCKO_DO_REG.
Input/Output Delay Switching Characteristics Added TIOL_IDELAY_RESOLUTION.
MMCM Switching Characteristics Extensive updates to table and notes including removal of TDESKEWMISMATCH_MMCM.
DPLL Switching Characteristics Extensive updates to table and notes including removal of TDESKEWMISMATCH_DPLL.
XPLL Switching Characteristics Extensive updates to table and notes including removal of TDESKEWMISMATCH_XPLL.
Device Pin-to-Pin Output Parameter Guidelines Updated the XCVM1802 parameters in Vivado Design Suite 2020.3 v2.00.
Device Pin-to-Pin Input Parameter Guidelines Updated the XCVM1802 parameters in Vivado Design Suite 2020.3 v2.00.
Package Parameter Guidelines Updated the XCVM1802 package skew in Vivado Design Suite 2020.3 v2.00.
DDR4 and LPDDR4/4X Memory Interface Controller Added Notes 2 and 3. Updated Note 6.
GTY and GTYP Transceiver DC Input and Output Levels Revised VIN in Table 1. Updated the specifications in Table 3.
GTY and GTYP Transceiver Performance Updated the FGTYLRANGE values.
GTY and GTYP Transceiver PLL/Lock Time Adaptation Added conditions to TLOCK.
GTY and GTYP Transceiver Transmitter and Receiver Switching Characteristics Removed legacy content and updated the applicable symbols, conditions, and values in both the Transmitter and Receiver tables.
GTY and GTYP Transceiver Electrical Compliance Added the table.
PMC Quad-SPI Controller Interface Added additional load information to the table.
Integrated Block for MRMAC Changed title and added specifications.
Programmable Logic Integrated Block for PCIe Added Table 1.
7/16/2020 Version 1.0
Initial release. N/A