TIDELAY_RESOLUTION/
TODELAY_RESOLUTION
|
X5IO IDELAY/ODELAY delay tap resolution for VM2152 only |
VM2152 |
N/A |
0.86 to 4.00
1
|
N/A |
0.86 to 4.00
1
|
ps |
XPHY IDELAY/ODELAY delay tap resolution |
All other devices |
1.22 to 4.00 |
ps |
TIDELAY_ERROR/ TODELAY_ERROR
|
X5IO calibrated delay line error (DELAY_VALUE) for VM2152 only |
VM2152 |
N/A |
–10 to +10
|
N/A |
–10 to +10
|
Delay Taps |
XPHY calibrated delay line error (DELAY_VALUE) (REFCLK_FREQUENCY = 500 to 1800
MHz)
2
|
All other devices |
–10 to +10 |
Delay Taps |
TIOL_IDELAY_RESOLUTION/TIOL_ODELAY_RESOLUTION
|
IOL IDELAY/ODELAY uncalibrated delay tap resolution for IOL
resources (HD or XP) |
All devices |
60 to 173 |
ps |
- For 800 MHz ≤ REFCLK_FREQUENCY ≤ 1600
MHz, set the PDL_CASCADE = TRUE. For REFCLK_FREQUENCY >1600 MHz, set the
PDL_CASCADE = FALSE. Refer to the
Versal
Adaptive SoC SelectIO Resources Architecture Manual (AM010). IDELAY is used for alignment and ALIGN_DELAY effects the
programmed DELAY_VALUE programming.
- For REFCLK_FREQUENCY < 500 MHz, BISC
calibration of the DELAY_VALUE_<0-5> is not guaranteed. Use the TIDELAY_RESOLUTION/TODELAY_RESOLUTION for delay calculations. Refer to the
Versal
Adaptive SoC SelectIO Resources Architecture Manual (AM010). IDELAY is used for
alignment and ALIGN_DELAY effects the programmed DELAY_VALUE programming.
|