Input/Output Delay Switching Characteristics - DS956

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID
DS956
Release Date
2025-01-13
Revision
1.14 English
Table 1. Input/Output Delay Switching Characteristics
Symbol Description Devices Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-3 -2 -2 -1 -2LLI -2 -1
TIDELAY_RESOLUTION/ TODELAY_RESOLUTION X5IO IDELAY/ODELAY delay tap resolution for VM2152 only VM2152 N/A 0.86 to 4.00 1 N/A 0.86 to 4.00 1 ps
XPHY IDELAY/ODELAY delay tap resolution All other devices 1.22 to 4.00 ps
TIDELAY_ERROR/ TODELAY_ERROR X5IO calibrated delay line error (DELAY_VALUE) for VM2152 only VM2152 N/A –10 to +10 N/A –10 to +10 Delay Taps
XPHY calibrated delay line error (DELAY_VALUE) (REFCLK_FREQUENCY = 500 to 1800 MHz) 2 All other devices –10 to +10 Delay Taps
TIOL_IDELAY_RESOLUTION/TIOL_ODELAY_RESOLUTION IOL IDELAY/ODELAY uncalibrated delay tap resolution for IOL resources (HD or XP) All devices 60 to 173 ps
  1. For 800 MHz ≤ REFCLK_FREQUENCY ≤ 1600 MHz, set the PDL_CASCADE = TRUE. For REFCLK_FREQUENCY >1600 MHz, set the PDL_CASCADE = FALSE. Refer to the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). IDELAY is used for alignment and ALIGN_DELAY effects the programmed DELAY_VALUE programming.
  2. For REFCLK_FREQUENCY < 500 MHz, BISC calibration of the DELAY_VALUE_<0-5> is not guaranteed. Use the TIDELAY_RESOLUTION/TODELAY_RESOLUTION for delay calculations. Refer to the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). IDELAY is used for alignment and ALIGN_DELAY effects the programmed DELAY_VALUE programming.