Device Pin-to-Pin Output Parameter Guidelines

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID
DS956
Release Date
2024-04-30
Revision
1.11 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol Description 1, 2 Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -1MM -2LLI -2LSE

-2LLE

-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
TICKOFMMCM Global clock input and output flip-flop with MMCM XCVM1102 N/A 6.08 6.60 7.06 N/A 7.27 7.33 7.94 ns
XQVM1102 N/A N/A       N/A N/A   ns
XCVM1302 N/A 6.29 6.82 7.27 N/A 7.48 7.49 8.08 ns
XCVM1402 N/A 6.74 7.30 7.76 N/A 7.96 7.96 8.56 ns
XQVM1402 N/A N/A 7.30 7.76 7.83 N/A N/A 8.56 ns
XCVM1502 N/A 6.97 7.52 7.98 N/A 8.21 8.21 8.81 ns
XQVM1502 N/A N/A 7.52 7.98 8.04 N/A N/A 8.81 ns
XCVM1802 N/A 7.37 8.07 8.56 N/A 8.73 8.73 9.37 ns
XQVM1802 N/A N/A 8.07 8.56 8.67 N/A N/A 9.37 ns
XCVM2202 N/A 6.73 7.31 7.78 N/A 7.93 8.00 8.61 ns
XCVM2302 5.69 N/A 6.26 6.56 N/A N/A 6.33 6.64 ns
XCVM2502 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XCVM2902 7.18 N/A 7.78 8.25 N/A N/A 8.47 9.08 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  2. MMCM output jitter is already included in the timing calculation.