DPLL Switching Characteristics

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID
DS956
Release Date
2024-04-30
Revision
1.11 English
Table 1. DPLL Specification
Symbol Description 1 Performance as a Function of Speed Grade and Operating Voltage (VCC_RAM) 2 Units
0.88V (H) 0.80V (M) 0.80V (L) 2
-3 -2 -2 -1 -2 -1
FINMAX_DPLL Maximum input clock frequency 3 1150 1150 1070 984 800 680 MHz
FINMIN _DPLL Minimum input clock frequency 50 50 50 50 50 50 MHz
FINJITTER _DPLL Maximum input clock jitter 4 < 20% of clock input period or 1 ns Max
FINDUTY_DPLL Input duty cycle range: 50–399 MHz 35–65 %
Input duty cycle range: 400–499 MHz 40–60 %
Input duty cycle range: >500 MHz 45–55 %
FPSCLKMAX_DPLL Maximum dynamic phase shift clock frequency 550 500 500 450 500 450 MHz
FPSCLKMIN_DPLL Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 0.01 0.01 MHz
FDCOMAX_DPLL Maximum DPLL DCO frequency 4000 4000 4000 4000 4000 4000 MHz
FDCOMIN_DPLL Minimum DPLL DCO frequency 2000 2000 2000 2000 2000 2000 MHz
FBANDWIDTH_DPLL DPLL bandwidth at typical 5 1.00 1.00 1.00 1.00 1.00 1.00 MHz
TSTATPHAOFFSET_DPLL Static phase offset of the DPLL outputs 6 0.12 0.12 0.12 0.12 0.12 0.12 ns
TOUTJITTER_DPLL DPLL output jitter Note 7
TOUTDUTY_DPLL DPLL output clock duty cycle precision 8 0.165 0.20 0.20 0.20 0.20 0.20 ns
TLOCKMAX_DPLL DPLL maximum lock time (non-deskew mode) Note 9
TLOCKDESKEWMAX_DPLL DPLL maximum lock time in deskew mode 10 Note 11
FOUTMAX_DPLL DPLL maximum output clock frequency 3 1150 1150 1070 984 800 680 MHz
FOUTMIN_DPLL DPLL minimum output clock frequency 5 5 5 5 5 5 MHz
TPWRDWNMINPULSE_DPLL Minimum power-down pulse width 5.00 5.00 5.00 5.00 5.00 5.00 ns
FTDCMAX_DPLL Maximum frequency at the time to digital converter 200 200 200 200 200 200 MHz
FTDCMIN_DPLL Minimum frequency at the time to digital converter 50 50 50 50 50 50 MHz
TDESKEWTAPDELAY_DPLL Nominal tap-delay of the programmable delay in the PD based deskew scheme 10 Note 12
  1. In the VM1802 device, the DPLLs (DPLL_X3Y7 and DPLL_X12Y7 sites) at the HDIO banks are not supported. Thus, DPLL ZHOLD mode for HDIO is not supported in these devices.
  2. The DPLLs are powered by the VCC_RAM supply, except for the DPLLs at HDIO banks are powered by the VCCINT supply. The VCC_RAM supply operates at 0.80V in low (L) voltage operation, see Table 1 .
  3. The maximum input and output clock frequencies are limited by the global clock buffers. See Table 1 .
  4. CLKIN jitter also applies to CLKIN_DESKEW and CLKFB_DESKEW in digital compensation. CLKFBIN applies only to analog compensation. This parameter is in regards to the functionality of the DPLL. Input jitter above ~1 MHz is reduced by the filtering properties of the DPLL. The magnitude of the reduction is found in the Vivado timing report.
  5. The DPLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
  6. The static offset is measured between any DPLL outputs with identical phase.
  7. Values for this parameter are available in the Vivado timing summary as part of the clock uncertainty equation.
  8. Includes global clock buffer.
  9. The maximum lock time in non-deskew mode is given by the given formula: Lock time in non-deskew mode in ms = 153.6 × DIVCLK_DIVIDE / (CLKIN_FREQUENCY in MHz).
  10. In the VM1802 device, the DPLL deskew functions are not supported.
  11. The maximum lock time in deskew mode is given by the following formula: Lock time in deskew mode in ms = (0.208 x (VCO_frequency in MHz) / (CLKIN_DESKEW_frequency in MHz)2) + (maximum lock time in non-deskew mode in ms from Note 9).
  12. The value for this parameter is included in compensation delay calculations.