If the design takes more than 1 cycle to complete operation, a clock-enable port
(ap_ce) can optionally be added to the entire block
using the
config_interface
command, or in the Vitis HLS GUI using the command.
The operation of the reset is described in Controlling Initialization and Reset Behavior, and can be modified using the
config_rtl
command, also available in the Solutions
Settings dialog box.