The vector data type is provided to easily model and synthesize
single instruction multiple data (SIMD) type operations. Many operators are
overloaded to provide SIMD behavior for vector types. The AMD Vitis™ HLS library provides the reference implementation for the
hls::vector<T, N>
type which represent a
single-instruction multiple-data (SIMD) vector, as defined below.
-
T
: The type of elements that the vector holds, can be a user-defined type which must provide common arithmetic operations. -
N
: The number of elements that the vector holds, must be a positive integer. - The best performance is achieved when both the bit-width of
T
andN
are integer powers of 2.
Vitis HLS provides a template type
hls::vector
that can be used to define SIMD
operands. All the operation performed using this type are mapped to hardware during
synthesis that will execute these operations in parallel. These operations can be
carried out in a loop which can be pipelined with II=1. The following example shows
how an eight element vector of integers is defined and used:
typedef hls::vector<int, 8> t_int8Vec;
t_int8Vec intVectorA, intVectorB;
.
.
.
void processVecStream(hls::stream<t_int8Vec> &inVecStream1,hls::stream<t_int8Vec> &inVecStream2, hls::stream<int8Vec> &outVecStream)
{
for(int i=0;i<32;i++)
{
#pragma HLS pipeline II=1
t_int8Vec aVec = inVecStream1.read();
t_int8Vec bBec = inVecStream2.read();
//performs a vector operation on 8 integers in parallel
t_int8Vec cVec = aVec * bVec;
outVecStream.write(cVec);
}
}
Refer to HLS Vector Library for additional information. Refer to Vitis-HLS-Introductory-Examples/Modeling/using_vectors on Github for an example.