Enabling the Vitis Kernel Flow - 2023.1 English

When you select the Vitis Kernel Flow Target on the Solution Settings dialog box, as discussed in Creating a New Vitis HLS Project, you are configuring Vitis HLS to generate the compiled kernel object (.xo) for the Vitis application acceleration flow, or heterogeneous compute flow.

The Vitis Kernel flow is more restrictive than the Vivado IP flow, and the kernels produced by the HLS tool must meet the specific requirements of the platforms and Xilinx Runtime (XRT), as described in PL Kernel Properties in the Vitis Unified Software Platform Documentation .

When specifying open_solution -flow_target vitis, or enabling the Vitis Kernel Flow in the IDE, Vitis HLS implements interface ports using the AXI standard as described in Interfaces for Vitis Kernel Flow. If there are no existing INTERFACE pragmas or directives in the code, then the following interface protocols will be applied by default.

• AXI4-Lite interfaces (s_axilite) are assigned to scalar arguments, control signals for arrays, and the return value of the software function.
• AXI4 Master interfaces (m_axi) are assigned to pointer and array arguments of the C/C++ function.
• Vitis HLS automatically tries to infer BURST transactions whenever possible to aggregate memory accesses to maximize the throughput bandwidth and/or minimize the latency.
• Defining a software function argument using an hls::stream data type implies an AXI4-Stream (axis) port.