Description
The set_directive_bind_storage
command assigns a variable (array, or function argument) in the code to a specific
memory type (type
) in the RTL. If the command is
not specified, the Vitis HLS tool determines the
memory type to assign. The HLS tool implements the memory using specified
implementations (impl
) in the hardware. For
example, you can use the set_directive_bind_storage
command to specify which type of memory,
and which implementation to use for an array variable. Also, this allows you to
control whether the array is implemented as a single or a dual-port RAM.
-storage_type
and
-storage_impl
options of the INTERFACE pragma
or directive.You can use the -latency
option to
specify the latency of the implementation. For block RAMs on the interface, the
-latency
option allows you to model off-chip,
non-standard SRAMs at the interface, for example supporting an SRAM with a latency
of 2 or 3. For internal operations, the -latency
option allows the operation to be implemented using more pipelined stages. These
additional pipeline stages can help resolve timing issues during RTL synthesis.
-latency
option, the operation must have an
available multi-stage implementation. The HLS tool provides a multi-stage
implementation for all block RAMs.For best results, AMD
recommends that you use -std=c99
for C and -fno-builtin
for C and C++. To specify the C compile
options, such as -std=c99
, use the Tcl command
add_files
with the -cflags
option. Alternatively, select the Edit CFLAGs button in the Project Settings dialog box as described in Creating a New Vitis HLS Project.
Syntax
set_directive_bind_storage [OPTIONS] <location> <variable>
-
<location>
is the location (in the formatfunction[/label]
) which contains the variable. -
<variable>
is the variable to be assigned.Tip: If the variable is an argument of a top-level function, then use the-storage_type
and-storage_impl
options of the INTERFACE pragma or directive.
Options
-
-type
- Defines the type of memory to bind to the specified variable.
-
-impl <value>
- Defines the implementation for the specified memory type.
Supported implementations include:
bram
,bram_ecc
,lutram
,uram
,uram_ecc
,srl
,memory
, andauto
as described below. -
-latency <int>
- Defines the default latency for the binding of the storage
type to the implementation. The valid latency varies according to the
specified
type
andimpl
. The default is -1, which lets Vitis HLS choose the latency.
Type | Implementation | Min Latency | Max Latency |
---|---|---|---|
FIFO | BRAM | 0 | 0 |
FIFO | LUTRAM | 0 | 0 |
FIFO | MEMORY | 0 | 0 |
FIFO | SRL | 0 | 0 |
FIFO | URAM | 0 | 0 |
RAM_1P | AUTO | 1 | 3 |
RAM_1P | BRAM | 1 | 3 |
RAM_1P | LUTRAM | 1 | 3 |
RAM_1P | URAM | 1 | 3 |
RAM_1WNR | AUTO | 1 | 3 |
RAM_1WNR | BRAM | 1 | 3 |
RAM_1WNR | LUTRAM | 1 | 3 |
RAM_1WNR | URAM | 1 | 3 |
RAM_2P | AUTO | 1 | 3 |
RAM_2P | BRAM | 1 | 3 |
RAM_2P | LUTRAM | 1 | 3 |
RAM_2P | URAM | 1 | 3 |
RAM_S2P | BRAM | 1 | 3 |
RAM_S2P | BRAM_ECC | 1 | 3 |
RAM_S2P | LUTRAM | 1 | 3 |
RAM_S2P | URAM | 1 | 3 |
RAM_S2P | URAM_ECC | 1 | 3 |
RAM_T2P | BRAM | 1 | 3 |
RAM_T2P | URAM | 1 | 3 |
ROM_1P | AUTO | 1 | 3 |
ROM_1P | BRAM | 1 | 3 |
ROM_1P | LUTRAM | 1 | 3 |
ROM_2P | AUTO | 1 | 3 |
ROM_2P | BRAM | 1 | 3 |
ROM_2P | LUTRAM | 1 | 3 |
ROM_NP | BRAM | 1 | 3 |
ROM_NP | LUTRAM | 1 | 3 |
set_directive_bind_storage
.Examples
In the following example, the coeffs[128]
variable is an argument to the function func1
. The
directive specifies that coeffs
uses a single port
RAM implemented on a BRAM core from the library.
set_directive_bind_storage -impl bram "func1" coeffs RAM_1P
coeffs
are defined in
the RAM_1P core.