Design Topology - 2022.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2022.2 English

In the Vitis core development kit, targeted devices can include Xilinx® MPSoCs, Kria™ SOMs, Versal ACAPs, or UltraScale+™ FPGAs. The FPGA contains a programmable region that implements and executes a device binary (.xclbin) file that contains and connects hardware kernels as compiled Xilinx object (.xo) files and AI Engine graphs when appropriate.

The extensible FPGA platform contains one or more interfaces to global memory (DDR or HBM), and optional streaming interfaces (to other user-defined PL resources such as external I/Os).

PL kernels can access data through memory interfaces (m_axi) or streaming interfaces (axis). The memory interfaces of PL kernels must be connected to memory interfaces of the extensible platform. The streaming interfaces of PL kernels can be connected to any streaming interfaces of the platform, of other PL kernels, or of the AI Engine array. Both memory-based and streaming connections are defined through Vitis linking options, as described in Linking the Kernels.

Multiple kernels (.xo) can be implemented in the PL of the Xilinx device binary (.xclbin), allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances of a kernel is programmable, and determined by linking options specified when building the FPGA binary. .

For Versal AI Core devices the .xclbin file can also contain the AI Engine graph application (libadf.a). The libadf.a and PL kernels (.xo) are linked with the target platform (.xpfm) to define the hardware design. The AI Engine can be driven by PL kernels through axis interfaces. The AI Engine can also be controlled through the Arm processor (PS) via run-time parameters (RTP) in the graph and GMIO on Versal ACAP devices. Refer to Versal ACAP AI Engine Programming Environment User Guide (UG1076) for more information.