VSC mode when compiled for the hardware emulation target (
-t hw_emu) will generate RTL from the accelerator sources
and run RTL simulation along with the application layer code. To view simulation
waveforms the user can enable the following switch in the xrt.ini file:
[Emulation]
debug_mode=guiFigure 1. Simulation Waveform View
The picture above shows the waveforms viewer in the Vivado XSim interface. By default, VSC will create
grouped waveform objects corresponding to the compute() interface. The kernel code must have been compiled with -g flag,
otherwise the grouping will error out in Vivado
XSim. In this design, there are four instances (NCU=4) of the accelerator enumerated as
grouped objects vadd*CU_0 through vadd*_CU_3. Each of these groups further contains the
signals that correspond to compute() arguments,
in1, in2,
out, and size.
The group kernel_execution is also auto-created and
contains the ap_start and ap_done signals for each CU instance.
Tip: In hardware emulation, the timing of
the start signals is not timing accurate with respect to realistic hardware behavior.
This is because interactions of the host with the emulation model (data transfer latency
over PCIe or with DDR/HBM memories), and application will not reflect real-time hardware
execution behavior. However, the timing from the start to a stop of a
compute() call is cycle-accurate.