External RTL traffic generators are used to drive traffic to Vitis emulation process or AI Engine simulation process using SystemVerilog or Verilog modules.
Figure 1. Test Bench Hierarchy
As shown in the figure above, the external test bench (on the left) and the Vitis emulation (on the right), both run as separate simulation processes. To establish communication between two processes using IPC, you must instantiate SIM_IPC Master/Slave modules.
Perform the following modifications:
- You need to create a project in Vivado simulator. For details on how to create a project, refer Vivado Design Suite User Guide: Design Flows Overview (UG892)
- Once the project is created, you need to instantiate
sim_ipc
IP in the external SV/Verilog testbench. - Then run the
export_simulation
command in Vivado to generate the scripts for the simulation - Run the simulation in Vivado simulator. For details running simulation refer to Vivado Design Suite User Guide: Logic Simulation (UG900)