Adding Traffic Generators to Your Design - 2022.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2022.2 English

Xilinx devices have rich I/O interfaces. Your platform can have memory interfaces (e.g DDR) which have their own specific model. However, your platforms could also have other I/Os, for example GT-kernel based generic I/O, Video Streams, and Sensor data. I/O Traffic Generator kernels provide a method for platforms and applications to inject traffic onto the I/O during simulation.

This solution requires both the inclusion of streaming I/O kernels (XO) or IP in your design, and the use of a Python/C++/C provided by Xilinx to inject traffic or to capture output data from the emulation process. The Xilinx provided Python/C++/C library can be used to integrate traffic generator code into your application, run it as a separate process, and have it interface with the emulation process. Currently, Xilinx provides a library that enables interfacing at AXI4-Stream level to mimic any Streaming I/O for software and hardware emulation and AXI3/AXI4 memory mapped interface to mimic any memory mapped I/O for hardware emulation.