DTG Settings - 2022.2 English

Figure 1. DTG Settings

Machine Name

For custom boards, do not change the configuration. For Xilinx® evaluation boards, see Table 1.

Extra dts/dtsi file

Provide the extra device tree files path separated with space. This config should be set with dts/dtsi absolute/full path. Provided dts/dtsi will be build as part of device-tree and deploy into /boot/devicetree.

Note: All dtsi files which are included in the dts file should be added to this config. For example, the zynqmp-test.dts file includes the custom.dtsi and main.dtsi files and you must add all three of them separated by spaces to this config.

${PROOT}/project-spec/dts_dir/zynqmp-test.dts
				${PROOT}/project-spec/dts_dir/custom.dtsi
				${PROOT}/project-spec/dts_dir/main.dtsi

Kernel Bootargs

The Kernel Bootargs sub-menu allows you to let PetaLinux automatically generate the kernel boot command-line settings in DTS, or pass PetaLinux user defined kernel boot command-line settings. The following are the default bootargs.

Microblaze -- console=ttyS0,115200 earlyprintk

zynq            -- console=ttyPS0,115200 earlyprintk
zynqmp          -- console=ttyPS0,115200 earlycon clk_ignore_unused root=/dev/ram0 rw
versal          -- console=ttyAMA0earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused

Note: If you want to see kernel panic prints on the console for Zynq UltraScale+ MPSoCs and Versal devices, add

earlycon
					console=<device>,<baud rate> clk_ignore_unused root=/dev/ram
					rw

. For example,

earlycon
					console=/dev/ttyPS0,115200 clk_ignore_unused root=/dev/ram rw

is added in the system_user.dtsi.

For more information, see kernel documentation.

Device Tree Overlay Configuration for Versal ACAPs, Zynq-7000 Devices, and Zynq UltraScale+ MPSoCs

If you want to load PL after Linux boot, select this option to separate PL from base DTB and build the pl.dtsi to generate pl.dtbo. After creating a PetaLinux project follow the steps to add overlay support:

Go to cd <proj root directory>.
In the petalinux-config command, select DTG Settings > Device tree overlay.
Use the pl-custom.dtsi(<plnx-proj-root>/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi) file to add or modify the PL nodes in pl.dtsi generated using the base XSA file. These dtsi changes will take effect when the Device tree overlay is enabled in petalinux-config.
Run petalinux-build to generate the pl.dtbo in images/linux directory.
FPGA manager overrides all the options of the device tree overlay. Device Tree Overlay will come into play only when FPGA manager is not selected.

Converting Bitstream from .bit to .bin

Create a bif file with the following content:

all: 
{
        [destination_device = pl] <bitstream in .bit> ( Ex: system.bit ) 
}

Run following command:

bootgen -image bitstream.bif -arch zynqmp -process_bitstream bin

Note: The bit/bin file name should be same as the firmware name specified in pl.dtsi (design_1_wrapper.bit.bin).

Removing PL from the Device Tree

Select this configuration option to skip PL nodes if the user does not depend on the PL IPs. Also, if any PL IP in DTG generates an error then you can simply enable this flag and the DTG will not generate any PL nodes.

Go to cd <proj root directory>.
In the petalinux-config command, select DTG Settings > Remove PL from device tree.
Run petalinux-build.

Note: FPGA manager overrides all the Remove PL options. Remove PL will comes into play only when FPGA manager is not selected.

Note: If you select both the device tree overlay and remove the PL from the device tree, then the base DTB will have an entry for overlay support but there is no pl.dtbo will be generated.