Performing Power Optimization in the Vivado Integrated Design Environment - 2022.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)
Document ID
UG907
Release Date
2022-04-26
Version
2022.1 English
Power optimizations are performed during two stages in Vivado:
  • opt_design
  • power_opt_design
Optimizations that are performed during the opt_design phase occur without user intervention. These optimizations primarily focus on power savings on block RAMs.
Important: The power optimization might impact the timing performance of your design during opt_design, power_opt_design, or both.

For UltraScale™ devices, the more aggressive block RAM power optimizations that may negatively impact timing are included only in power_opt_design. This allows performance to be traded for power savings. For UltraScale+™ devices, XPM-URAM power optimization occurs in power_opt_design.

By default the opt_design command performs block RAM power optimization. Block RAM power optimization can also be run explicitly and standalone by using the -bram_power_opt option:
opt_design -bram_power_opt
To disable block RAM power optimization from the default opt_design flow, set the NoBramPowerOpt directive to the opt_design command:
opt_design -directive NoBramPowerOpt

You can also set this directive in the Implementation settings window as shown in the following figure.

Figure 1. Disabling block RAM Power Optimization During Opt Design

To enable power optimization through power_opt_design in the Vivado® Integrated Design Environment, check the is_enabled option available by selecting Tools > Project Settings > Implementation > Power Opt Design as shown in the following figure. Once enabled, power optimization is run as a part of the implementation step in the Vivado Integrated Design Environment. To set fine grained control over optimization and to report the result of the optimization, refer to the Power Analysis Tcl Commands section.

Important: Power Opt Design can be enabled either pre-place or post-place in the design flow, but not in both places. See Running Power Optimization for more details.
Figure 2. Power Optimization Option