Power Optimization Feature - 2022.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2022.1 English

The Vivado® design tools offer a variety of power optimizations to minimize dynamic power consumption by up to 30% in your design. These optimizations use ASIC style clock gating techniques to minimize activity on portions of the design that do not contribute to the design output or those that do not require design state update for that clock cycle. These optimizations can be applied on the entire design or on selected portions of the design as shown in the following figure.

The dynamic power consumption of a device is determined by the operating clock frequency (f), node capacitance (C), device operating voltage (V), and the activity (α) on various nodes in the design. For most designs, several of the above parameters are typically fixed either by the device technology (for example, voltage) or by design requirements (for example, operating frequency). However, there are several nodes in the design that do not affect the output of the device but still continue to toggle. This constitutes a significant portion of wasted dynamic power. You can use the clock enables (CE) in the device for gating such nodes. While this is possible through optimal coding techniques, this is rarely done by the designer either because the design contains intellectual property (IP) from other sources or because of the amount of effort involved in performing such fine grained clock gating. Vivado automates these power optimizations under a single command to maximize power savings while minimizing your effort.

Vivado performs an analysis on the entire design, including legacy and third-party IP blocks, for potential power savings. It looks at the output logic of sourcing registers that do not contribute to the result for each clock cycle and then creates fine-grained clock gating and/or logic gating signals that neutralize unnecessary switching activity.

Figure 1. Intelligent Clock Gating

The intelligent clock gating optimization also reduces power for dedicated block RAM in either simple dual-port or true dual-port mode as shown in the following figure. These blocks provide several enables: an array enable, a write enable, and an output register clock enable. Most of the power savings comes from using the array enable, and the software implements functionality to reduce power when no data is being written and when the output is not being used.

Figure 2. Clock Gating Optimizations Using Block RAM Enables

Xilinx® intelligent clock gating optimizations do not modify user logic but instead create additional gating logic. Therefore the functionality of the design is preserved at all times. However, this optimization could impact timing, especially if the optimization is applied on critical paths.