Experiment within Xilinx Power Estimator (XPE) - 2022.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2022-04-26
Version
2022.1 English

In XPE you can import the Vivado® power analysis results from modules developed by multiple sources to review the total power once these separate IP blocks are implemented in the device. You can also evaluate situations where you would have to change the netlist, and evaluate the power implications, without having to actually make the code changes. For your design core logic, XPE works at a coarser resolution than the Vivado power analysis, because you cannot adjust each logic element or signal individually in XPE. In XPE, you can also experiment with:

Resource usage
Explore reducing the resource count. Try remapping pieces of logic from slice logic to dedicated blocks such as block RAM or DSP, and vice versa.
Resource configuration
Explore using different configuration settings for the design I/Os, block RAMs, clock generators, and other resources.