DDR Memory Controller (DDRMC) - 2022.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2022.1 English

Versal® ACAP devices have a hardened DRAM controller available up to a maximum of 4. This can be accessed from the PS or the PL. However, the connection must go through the NoC. The DRAM memory controller can only be accessed using NoC. Each memory controller instance is connected to the NoC using four system ports. Each of these ports are bi-directional 128-bit data paths with three traffic types. A maximum data rate of 4266 Mb/s, per data pin, is supported for LPDDR4/4X and a maximum data rate of 3200 Mb/s is supported for DDR4/4E. For more information, see Memory Interface Controller section of Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956). The DDRMC configuration is performed using NoC IP and the dependent power parameters are computed using NoC compiler. For more information, see Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The following figure shows the DDRMC Power View.

Figure 1. DDRMC Power View
Note: NoC and DDRMC power can be reported during the post synthesis and post implementation stages of the design. In the project flow, Xilinx® suggests that you should use the Tcl command update_noc_qos after opening a synthesized or implemented design to report NoC and DDRMC Power.