PS-PMC - 2022.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
Release Date
2022.1 English

VersalĀ® devices feature a Control Interface and Processing System IP core. This subsystem is used to configure PL, NoC, and AI Engine. The Control Interface & Processing System is divided into the following power domains. These power domains can operate independently.

Platform Management Controller (PMC)
PMC is always on. It is used for device configuration and management. The PMCIOs are a part of this domain. PMC is powered by VCC_PMC rail.
Full Power Domain (FPD)
This domain consists of application processing units (APUs) such as Dual A72 Core, L2 Cache, FPD Interconnect, and CCIX. FPD is powered by VCC_PSFP rail.
Low Power Domain (LPD)
This domain consists of real-time processing units such as Dual R5, TCM , OCM, and LPD Interconnect. LPD is powered by VCC_PSLP. PSIOs (Dual GEM, USB, and other IO's) are a part of this domain. The IO supply required for the LPD is VCCO_502 and it depends on the type of PSIO used.

Following are the parameters which can be modified using Control Interface and Processing System (CIPS) IP core configuration wizard in Vivado.

  • PMC
    • PMC subsystem clock frequency and peripheral IO clocks can be modified.
  • FPD
    • A72 operation clock and FPD interconnect clocks.
  • LPD
    • Dual R5 Operating Clock and LPD Interconnect Clocks.
    • PS IO clocks like GEM and USB. IO standards for each bank can also be configured.

For more information, see Control, Interface and Processing System LogiCORE IP Product Guide (PG352).

Power numbers reported by report_power are for a default operating load of 90% for all processing systems including A72, R5, and PMC (also the interconnects ). For an IO power estimate, IOs need to be configured from the IP configuration wizard, if not it reports zero power for the IOs. The power reported for a PS instance is the sum of all the PS rails (VCC_PSFP, VCC_PSLP, and IOs).

Figure 1. PS View