Manually Parsing Design Files - 2021.2 English

Vivado Design Suite Tutorial: Logic Simulation

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2021.2 English

As an alternative to creating a Vivado® simulator project script, you can compile individual design source files directly from the command line using the xvlog or xvhdl commands to parse the design sources and write them to an HDL library. You could use this method for simple simulation runs, or to define a shell script and makefile compilation flow.

Parse individual or multiple Verilog files using the xvlog command with the following syntax format:

xvlog [options] <verilog_file | list_of_files>

Parse individual VHDL files using the xvhdl command with the following syntax format:

xvhdl [options] <VHDL_file>

For a complete list of available xvlog and xvhdl command options, see the Vivado Design Suite User Guide: Logic Simulation (UG900). The parse_standalone.bat file in <Extract_Dir>/scripts or <Extract_Dir>/completed provide examples of running xvlog and xvhdl directly.