Tutorial Description - 2021.2 English

Vivado Design Suite Tutorial: Logic Simulation

Document ID
Release Date
2021.2 English

This tutorial demonstrates a design flow in which you can use the Vivado® simulator for performing behavioral, functional, or timing simulation from the Vivado Integrated Design Environment (IDE).

Important: Tutorial files are configured to run the Vivado simulator in a Windows environment. To run elements of this tutorial under the Linux operating system, some file modifications may be necessary.

You can run the Vivado simulator in both Project Mode (using a Vivado design project to manage design sources and the design flow) and in Non-Project mode (managing the design more directly). For more information about Project Mode and Non-Project Mode, refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892).

The following figure shows a block diagram of the tutorial design.

Figure 1. Tutorial Design

The tutorial design consists of the following blocks:

  • A sine wave generator that generates high, medium, and low frequency sine waves; plus an amplitude sine wave (sinegen.vhd).
  • DDS compilers that generate low, middle, and high frequency waves: (sine_low.vhd, sine_mid.vhd, and sine_high.vhd).
  • A Finite State Machine (FSM) to select one of the four sine waves (fsm.vhd).
  • A debouncer that enables switch-selection between the raw and the debounced version of the sine wave selector (debounce.vhd).
  • A design top module that resets FSM and the sine wave generator, and then multiplexes the sine select results to the LED output (sinegen_demo.vhd).
  • A simple testbench (testbench.v) to initiate the sine wave generator design that:
    • Generates a 200 MHz input clock for the design system clock, sys_clk_p.
    • Generates GPIO button selections.
    • Controls raw and debounced sine wave select.
Note: For more information about testbenches, see Writing Efficient Test Benches (XAPP199).