Stepping Through Source Code - 2021.2 English

Vivado Design Suite Tutorial: Logic Simulation
Document ID
UG937
Release Date
2021-11-10
Version
2021.2 English
Another useful Vivado® simulator debug tool is the Line Stepping feature. With line stepping, you can run the simulator one-simulation unit (line, process, task) at a time. This is helpful if you are interested in learning how each line of your source code affects the results in simulation.

Step through the source code line-by-line and examine how the low frequency wave is selected, and whether the DDS compiler output is correct.

  1. On the Vivado simulator toolbar menu, click the Step button .

    The simulation steps forward to the next executable line, in this case in another source file. The fsm.vdh file is opened in the Text Editor. You may need to relocate the Text Editor to let you see all the windows as previously arranged.

    Note: You can also type the step command at the Tcl prompt.
  2. Continue to Step through the design, until the code returns to line 144 of sinegen.vhd.

    You have stepped through one complete cycle of the circuit. Notice in the Waveform window that while sel is 0, signal sine_l is assigned as a low frequency sine wave to the output sine. Also, notice that sine_l remains uninitialized.

  3. For debug purposes, initialize the value of sine_l by entering the following add_force command in the Tcl console:
    add_force /testbench/dut/U_SINEGEN/sine_l 0110011011001010

    This command forces the value of sine_l into a specific known condition, and can provide a repeating set of values to exercise the signal more vigorously, if needed. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information on using add_force.

  4. Continue the simulation by clicking the Run All button a few more times.

    In the Waveform window, notice that the value of sine_l[15:0] is now set to the value specified by the add_force command, and this value is assigned to the output signal sine[19:0] since the value of sel is still 0.

    Trace the sine_l signal in the HDL source files, and identify the input for sine_l.

  5. In the Text Editor, right-click to open the popup menu, and select the Find in files option to search for sine_l.
  6. Select the Match whole word and Enabled design sources checkboxes, as shown in the following figure, and click Find.

    The Find in Files results display at the bottom of the Vivado IDE, with all occurrences of sine_l found in the sinegen.vhd file.

  7. Expand the Find in Files results to view the results in the sinegen.vhd file.

    The second result, on line 111, identifies a problem with the design. At line 111 in the sinegen.vhd file, the m_axis_data_tdata_sine_low signal is assigned to sine_l. Since line 111 is commented out, the sine_l signal is not connected to the low frequency DDS compiler output, or any other input.

  8. Uncomment line 111 in the sinegen.vhd file, and click the Save File button .
  9. In the Tcl Console, remove the force on sine_l: remove_forces -all