There are separate project files and
sources for each of the labs in this tutorial. You can find these at the link provided
below or under Xilinx
website.
on the - Download the reference design files.
- Extract the zip file contents into any write-accessible location.
This tutorial refers to the extracted file contents of ug937-design-files directory as <Extract_Dir>.
Recommended: You modify the tutorial design data while working through this
tutorial. Use a new copy of the design files each time you start this
tutorial.
The following table describes the contents of the ug937-design-files.zip file.
Directories/Files | Description |
---|---|
/completed
|
Contains the completed files, and a Vivado 2021.x project of the tutorial design for
reference. (x denotes the latest version of Vivado 2021 IDE) |
/scripts
|
Contains the scripts you run during the tutorial. |
/sim
|
Contains the testbench.v file. |
/sources
|
Contains the HDL files necessary for the functional simulation. |
readme.txt
|
readme.txt is a readme file about the contents
and version history of this tutorial design. |
/uvm
|
UVM example needed for Lab 5 |