Primitive: Input Delay Element
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: DELAY
Introduction
The IDELAYE5 is an uncalibrated input delay element that can be connected to an input register/IDDR or driven directly into device logic. The IDELAYE5 is a 32-tap uncalibrated delay element that allows for incoming signals to be delayed on an individual basis. Refer to the device Data Sheet for delay values.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CASC_OUT | Output | 1 | Cascade delay output to ODELAYE5 input cascade. |
CASC_RETURN | Input | 1 | Cascade delay returning from ODELAYE5 DATAOUT. |
CE | Input | 1 | Active-High enable increment/decrement input. |
CLK | Input | 1 | Clock Input |
CNTVALUEIN<4:0> | Input | 5 | Counter value from device logic for dynamically loadable tap value input. |
CNTVALUEOUT<4:0> | Output | 5 | Counter value to device logic for reporting tap value of the delay element. |
DATAOUT | Output | 1 | Delayed data output from IDATAIN. |
IDATAIN | Input | 1 | Data input for IDELAYE5 from the IBUF. |
INC | Input | 1 | Increment/Decrement tap delay input. |
LOAD | Input | 1 | Load the value of CNTVALUEIN. |
RST | Input | 1 | Asynchronous Reset, active level based on IS_RST_INVERTED. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
CASCADE | STRING | "FALSE", "TRUE" | "FALSE" | The CASCADE attribute is set to TRUE when the ODELAYE5 is used to cascade the IDELAYE5. |
IS_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the CLK pin is active-High or active-Low. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the RST pin is active-High or active-Low. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IDELAYE5: Input Delay Element
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
IDELAYE5_inst : IDELAYE5
generic map (
CASCADE => "FALSE", -- Cascade setting (FALSE, TRUE)
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_RST_INVERTED => '0' -- Optional inversion for RST
)
port map (
CASC_OUT => CASC_OUT, -- 1-bit output: Cascade delay output to ODELAYE5 input cascade
CNTVALUEOUT => CNTVALUEOUT, -- 5-bit output: Counter value output
DATAOUT => DATAOUT, -- 1-bit output: Delayed data output
CASC_RETURN => CASC_RETURN, -- 1-bit input: Cascade delay returning from ODELAYE5 DATAOUT
CE => CE, -- 1-bit input: Active High enable increment/decrement input
CLK => CLK, -- 1-bit input: Clock Input
CNTVALUEIN => CNTVALUEIN, -- 5-bit input: Counter value input
IDATAIN => IDATAIN, -- 1-bit input: Data input from the IOBUF
INC => INC, -- 1-bit input: Increment / Decrement tap delay input
LOAD => LOAD, -- 1-bit input: Load CNTVALUEIN
RST => RST -- 1-bit input: Asynchronous Reset
);
-- End of IDELAYE5_inst instantiation
Verilog Instantiation Template
// IDELAYE5: Input Delay Element
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
IDELAYE5 #(
.CASCADE("FALSE"), // Cascade setting (FALSE, TRUE)
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_RST_INVERTED(1'b0) // Optional inversion for RST
)
IDELAYE5_inst (
.CASC_OUT(CASC_OUT), // 1-bit output: Cascade delay output to ODELAYE5 input cascade
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output
.CASC_RETURN(CASC_RETURN), // 1-bit input: Cascade delay returning from ODELAYE5 DATAOUT
.CE(CE), // 1-bit input: Active High enable increment/decrement input
.CLK(CLK), // 1-bit input: Clock Input
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
.IDATAIN(IDATAIN), // 1-bit input: Data input from the IOBUF
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
.LOAD(LOAD), // 1-bit input: Load CNTVALUEIN
.RST(RST) // 1-bit input: Asynchronous Reset
);
// End of IDELAYE5_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)