Primitive: 18 x 18 + 58 complex multiply accumulate block
- PRIMITIVE_GROUP: ARITHMETIC
- PRIMITIVE_SUBGROUP: DSP
Introduction
This design element uses two back to back DSP58 instances to create a versatile, scalable complex arithmetic unit. It can be used for 18 * 18 bit complex or complex conjugate multiplications. The adder/subtracter units after the multiplier can be used for up to 58-bit complex addition, subtraction or accumulation.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
Cascade: Cascade Ports. | |||
ACIN_IM<17:0> | Input | 18 | Cascaded data input from ACOUT_IN of previous DSPCPLX. |
ACIN_RE<17:0> | Input | 18 | Cascaded data input from ACOUT_RE of previous DSPCPLX. |
ACOUT_IM<17:0> | Output | 18 | Cascaded data output to ACIN_IM of next DSPCPLX. If not used, leave unconnected. |
ACOUT_RE<17:0> | Output | 18 | Cascaded data output to ACIN_RE of next DSPCPLX. If not used, leave unconnected. |
BCIN_IM<17:0> | Input | 18 | Cascaded data input from BCOUT_IM of previous DSPCPLX (multiplexed with B_IM). If not used, tie port to all zeros. |
BCIN_RE<17:0> | Input | 18 | Cascaded data input from BCOUT_RE of previous DSPCPLX (multiplexed with B_RE). If not used, tie port to all zeros. |
BCOUT_IM<17:0> | Output | 18 | Cascaded data output to BCIN_IM of next DSPCPLX. If not used, leave unconnected. |
BCOUT_RE<17:0> | Output | 18 | Cascaded data output to BCIN_RE of next DSPCPLX. If not used, leave unconnected. |
CARRYCASCIN_IM | Input | 1 | Cascaded carry input from CARRYCASCOUT_IM of previous DSPCPLX. |
CARRYCASCIN_RE | Input | 1 | Cascaded carry input from CARRYCASCOUT_RE of previous DSPCPLX. |
CARRYCASCOUT_IM | Output | 1 | Cascaded carry output to CARRYCASCIN_IM of next DSPCPLX. This signal is internally fed back into the CARRYINSEL_IM multiplexer input of the same DSPCPLX. |
CARRYCASCOUT_RE | Output | 1 | Cascaded carry output to CARRYCASCIN_RE of next DSPCPLX. This signal is internally fed back into the CARRYINSEL_RE multiplexer input of the same DSPCPLX. |
MULTSIGNIN_IM | Input | 1 | Sign of the imaginary multiplied result from the previous DSPCPLX block, or tie to ground if not used. |
MULTSIGNIN_RE | Input | 1 | Sign of the real multiplied result from the previous DSPCPLX block, or tie to ground if not used. |
MULTSIGNOUT_IM | Output | 1 | Sign of the multiplied result cascaded to the next DSPCPLX for MACC extension. Connect to the MULTSIGNIN_IM of another DSPCPLX block, or tie to ground if not used. |
MULTSIGNOUT_RE | Output | 1 | Sign of the multiplied result cascaded to the next DSPCPLX for MACC extension. Connect to the MULTSIGNIN_RE of another DSPCPLX block, or tie the MULTSIGNIN_RE of another DSPCPLX to ground if not used. |
PCIN_IM<57:0> | Input | 58 | Cascaded data input from PCOUT_IM of previous DSPCPLX to adder. If used, connect to PCOUT_IM of upstream cascaded DSPCPLX. If not used, tie port to all zeros. |
PCIN_RE<57:0> | Input | 58 | Cascaded data input from PCOUT_RE of previous DSPCPLX to adder. If used, connect to PCOUT_RE of upstream cascaded DSPCPLX. If not used, tie port to all zeros. |
PCOUT_IM<57:0> | Output | 58 | Cascaded data output to PCIN_IM of next DSPCPLX. If used, connect to PCIN_IM of downstream cascaded DSPCPLX. If not used, leave unconnected. |
PCOUT_RE<57:0> | Output | 58 | Cascaded data output to PCIN_RE of next DSPCPLX. If used, connect to PCIN_RE of downstream cascaded DSPCPLX. If not used, leave unconnected. |
Control: Control Inputs/Status Bits. | |||
ALUMODE_IM<3:0> | Input | 4 | Controls the selection of the logic function in the DSPCPLX. |
ALUMODE_RE<3:0> | Input | 4 | Controls the selection of the logic function in the DSPCPLX. |
CARRYINSEL_IM<2:0> | Input | 3 | Selects the carry source. |
CARRYINSEL_RE<2:0> | Input | 3 | Selects the carry source. |
CLK | Input | 1 | This port is the DSPCPLX input clock, common to all internal registers and flip-flops. |
CONJUGATE_A | Input | 1 | Select signal to select between A (CONJUGATE_A=0) or the conjugate of A (CONJUGATE_A=1). |
CONJUGATE_B | Input | 1 | Select signal to select between B (CONJUGATE_B=0) or the conjugate of B (CONJUGATE_B=1). |
OPMODE_IM<8:0> | Input | 9 | Controls the input to the W, X, Y, and Z multiplexers in the imaginary side of DSPCPLX dictating the operation or function of the component. |
OPMODE_RE<8:0> | Input | 9 | Controls the input to the W, X, Y, and Z multiplexers in the real side of DSPCPLX dictating the operation or function of the component. |
OVERFLOW_IM | Output | 1 | Active-High overflow indicator when used with the appropriate setting of the pattern detector and PREG_IM=1. |
OVERFLOW_RE | Output | 1 | Active-High overflow indicator when used with the appropriate setting of the pattern detector and PREG_RE=1. |
PATTERNBDETECT_IM | Output | 1 | Active-High match indicator between P_IM[57:0] and the pattern bar determined by SEL_PATTERN_IM. |
PATTERNBDETECT_RE | Output | 1 | Active-High match indicator between P_RE[57:0] and the pattern bar determined by SEL_PATTERN_RE. |
PATTERNDETECT_IM | Output | 1 | Active-High match indicator between P_IM[57:0] and the pattern gated by the MASK_IM. Result arrives on the same cycle as P_IM. |
PATTERNDETECT_RE | Output | 1 | Active-High match indicator between P[47:0] and the pattern gated by the MASK_RE. Result arrives on the same cycle as P_RE. |
UNDERFLOW_IM | Output | 1 | Active-High underflow indicator when used with the appropriate setting of the pattern detector and PREG_IM=1. |
UNDERFLOW_RE | Output | 1 | Active-High underflow indicator when used with the appropriate setting of the pattern detector and PREG_RE=1. |
Data: Data Ports. | |||
A_IM<17:0> | Input | 18 | 18-bit A_IM data input to the complex arithmetic unit. |
A_RE<17:0> | Input | 18 | 18-bit A_RE data input to the complex arithmetic unit. |
B_IM<17:0> | Input | 18 | The B_IM input of the Complex Arithmetic Unit. If this port is not used, tie all bits High. |
B_RE<17:0> | Input | 18 | The B_RE input of the Complex Arithmetic Unit. If this port is not used, tie all bits High. |
CARRYIN_IM | Input | 1 | Carry input from the device logic. |
CARRYIN_RE | Input | 1 | Carry input from the device logic. |
CARRYOUT_IM | Output | 1 | Carry output from the device logic. |
CARRYOUT_RE | Output | 1 | Carry output from the device logic. |
C_IM<57:0> | Input | 58 | Data input to the second-stage adder/subtracter, pattern detector, or logic function. If this port is not used, tie all bits High. |
C_RE<57:0> | Input | 58 | Data input to the second-stage adder/subtracter, pattern detector, or logic function. If this port is not used, tie all bits High. |
P_IM<57:0> | Output | 58 | Imaginary data output from second stage adder/subtracter or logic function. |
P_RE<57:0> | Output | 58 | Real data output from second stage adder/subtracter or logic function. |
Reset/Clock Enable: Reset/Clock Enable Inputs | |||
ASYNC_RST | Input | 1 | Asynchronous reset for all registers. Input is only valid when RESET_MODE=ASYNC. |
CEAD | Input | 1 | Active-High, clock enable for the pre-adder output AD pipeline register. Tie to logic one if not used and ADREG=1. Tie to logic zero if ADREG=0. |
CEALUMODE_IM | Input | 1 | Active-High, clock enable for ALUMODE_IM (control inputs) registers (ALUMODEREG_IM=1). Tie to logic one if not used. |
CEALUMODE_RE | Input | 1 | Active-High, clock enable for ALUMODE_RE (control inputs) registers (ALUMODEREG_RE=1). Tie to logic one if not used. |
CEA1_IM | Input | 1 | Active-High, clock enable for the first A_IM (input) register. This port is only used if AREG_IM=2. When two registers are used, this is the first sequentially. If the A port is not used, tie Low. |
CEA1_RE | Input | 1 | Active-High, clock enable for the first A_RE (input) register. This port is only used if AREG_RE=2. When two registers are used, this is the first sequentially. If the A port is not used, tie Low. |
CEA2_IM | Input | 1 | Active-High, clock enable for the second A_IM (input) register. When two registers are used, this is the second sequentially. When one register is used (AREG_IM=1), CEA2_IM is the clock enable. If the A_IM port is not used, tie Low. |
CEA2_RE | Input | 1 | Active-High, clock enable for the second A_RE (input) register. When two registers are used, this is the second sequentially. When one register is used (AREG_RE=1), CEA2_RE is the clock enable. If the A_RE port is not used, tie Low. |
CEB1_IM | Input | 1 | Active-High, clock enable for the first B_IM (input) register. When two registers are used, this is the first sequentially. If the B port is not used, tie Low. |
CEB1_RE | Input | 1 | Active-High, clock enable for the first BREG_RE (input) register. When two registers are used, this is the first sequentially. If the B port is not used, tie Low. |
CEB2_IM | Input | 1 | Active-High, clock enable for the second B_IM (input) register. This port is only used if BREG_IM=1 or 2. Tie to logic one if not used and BREG_IM=1 or 2. Tie to logic zero if BREG_IM=0. When two registers are used, this is the second sequentially. When one register is used (BREG_IM=1), CEB2_IM is the clock enable. |
CEB2_RE | Input | 1 | Active-High, clock enable for the second B_RE (input) register. This port is only used if BREG_RE=1 or 2. Tie to logic one if not used and BREG_RE=1 or 2. Tie to logic zero if BREG_RE=0. When two registers are used, this is the second sequentially. When one register is used (BREG_RE=1), CEB2_RE is the clock enable. |
CECARRYIN_IM | Input | 1 | Active-High, clock enable for the CARRYIN_IM (input from fabric) register (CARRYINREG_IM=1). Tie to logic one if not used. |
CECARRYIN_RE | Input | 1 | Active-High, clock enable for the CARRYIN_RE (input from fabric) register (CARRYINREG_RE=1). Tie to logic one if not used. |
CEC_IM | Input | 1 | Active-High, clock enable for the C_IM (input) register (CREG_IM=1). If the C_IM port is not used, tie Low. |
CECONJUGATE_A | Input | 1 | Active-High, clock enable for the CONJUGATE_A (input from fabric) register (CONJUGATEREG_A=1). Tie to logic one if not used. |
CECONJUGATE_B | Input | 1 | Active-High, clock enable for the CONJUGATE_B (input from fabric) register (CONJUGATEREG_B=1). Tie to logic one if not used. |
CEC_RE | Input | 1 | Active-High, clock enable for the C (input) register (CREG_RE=1). If the C_RE port is not used, tie Low. |
CECTRL_IM | Input | 1 | Active-High, clock enable for the OPMODE_IM and CARRYINSEL_IM (control inputs) registers (OPMODEREG_IM=1 or CARRYINSELREG_IM=1). Tie to logic one if not used. |
CECTRL_RE | Input | 1 | Active-High, clock enable for the OPMODE_RE and CARRYINSEL_RE (control inputs) registers (OPMODEREG_RE=1 or CARRYINSELREG_RE=1). Tie to logic one if not used. |
CEM_IM | Input | 1 | Active-High, clock enable for the post-multiply M_IM (pipeline) register and the internal multiply round CARRYIN_IM register (MREG_IM=1). Tie to logic one if not used. |
CEM_RE | Input | 1 | Active-High, clock enable for the post-multiply M_RE (pipeline) register and the internal multiply round CARRYIN_RE register (MREG_RE=1). Tie to logic one if not used. |
CEP_IM | Input | 1 | Active-High, clock enable for the P_IM (output) register (PREG_IM=1). Tie to logic one if not used. |
CEP_RE | Input | 1 | Active-High, clock enable for the P (output) register (PREG=1). Tie to logic one if not used. |
RSTA_IM | Input | 1 | Reset for both A_IM (input) registers (AREG_IM=1 or 2). Polarity is determined by the IS_RSTA_IM_INVERTED attribute. Tie to logic zero if A_IM port is not used. |
RSTAD | Input | 1 | Reset for both AD_IM and AD_RE registers (ADREG=1). Polarity is determined by the IS_RSTAD_INVERTED attribute. Tie to logic zero if ADREG=0. |
RSTALLCARRYIN_IM | Input | 1 | Reset for the Carry (internal path) and the CARRYIN_IM registers (CARRYINREG_IM=1). Polarity is determined by the IS_RSTALLCARRYIN_IM_INVERTED attribute. Tie to logic zero if not used. |
RSTALLCARRYIN_RE | Input | 1 | Reset for the Carry (internal path) and the CARRYIN_RE registers (CARRYINREG_RE=1). Polarity is determined by the IS_RSTALLCARRYIN_RE_INVERTED attribute. Tie to logic zero if not used. |
RSTALUMODE_IM | Input | 1 | Reset for ALUMODE_IM (control inputs) registers (ALUMODEREG_IM=1). Polarity is determined by the IS_RSTALUMODE_IM_INVERTED attribute. Tie to logic zero if not used. |
RSTALUMODE_RE | Input | 1 | Reset for ALUMODE_RE (control inputs) registers (ALUMODEREG_RE=1). Polarity is determined by the IS_RSTALUMODE_RE_INVERTED attribute. Tie to logic zero if not used. |
RSTA_RE | Input | 1 | Reset for both A_RE (input) registers (AREG_RE=1 or 2). Polarity is determined by the IS_RSTA_RE_INVERTED attribute. Tie to logic zero if A_RE port is not used. |
RSTB_IM | Input | 1 | Reset for both B_IM (input) registers (BREG_IM=1 or 2). Polarity is determined by the IS_RSTB_IM_INVERTED attribute. Tie to logic zero if B_IM port is not used. |
RSTB_RE | Input | 1 | Reset for both B_RE (input) registers (BREG_RE=1 or 2). Polarity is determined by the IS_RSTB_RE_INVERTED attribute. Tie to logic zero if B_RE port is not used. |
RSTC_IM | Input | 1 | Reset for the C_IM (input) registers (CREG_IM=1). Polarity is determined by the IS_RSTC_IM_INVERTED attribute. Tie to logic zero if C_IM port is not used. |
RSTCONJUGATE_A | Input | 1 | Reset for CONJUGATE_A (input) register (CONJUGATEREG_A=1). Polarity is determined by the IS_RSTCONJUGATE_A_INVERTED attribute. Tie to logic zero if CONJUGATE_A port is not used. |
RSTCONJUGATE_B | Input | 1 | Reset for CONJUGATE_B (input) register (CONJUGATEREG_B=1). Polarity is determined by the IS_RSTCONJUGATE_B_INVERTED attribute. Tie to logic zero if CONJUGATE_B port is not used. |
RSTC_RE | Input | 1 | Reset for the C_RE (input) registers (CREG_RE=1). Polarity is determined by the IS_RSTC_RE_INVERTED attribute. Tie to logic zero if C_RE port is not used. |
RSTCTRL_IM | Input | 1 | Reset for OPMODE_IM and CARRYINSEL_IM (control inputs) registers (OPMODEREG_IM=1 and/or CARRYINSELREG_IM=1). Polarity is determined by the IS_RSTCTRL_IM_INVERTED attribute. Tie to logic zero if not used. |
RSTCTRL_RE | Input | 1 | Reset for OPMODE_RE and CARRYINSEL_RE (control inputs) registers (OPMODEREG_RE=1 and/or CARRYINSELREG_RE=1). Polarity is determined by the IS_RSTCTRL_RE_INVERTED attribute. Tie to logic zero if not used. |
RSTM_IM | Input | 1 | Reset for the M_IM (pipeline) registers (MREG_IM=1). Polarity is determined by the IS_RSTM_IM_INVERTED attribute. Tie to logic zero if not used. |
RSTM_RE | Input | 1 | Reset for the M_RE (pipeline) registers (MREG_RE=1). Polarity is determined by the IS_RSTM_RE_INVERTED attribute. Tie to logic zero if not used. |
RSTP_IM | Input | 1 | Reset for the P_IM (output) registers (PREG_IM=1). Polarity is determined by the IS_RSTP_IM_INVERTED attribute. Tie to logic zero if not used. |
RSTP_RE | Input | 1 | Reset for the P_RE (output) registers (PREG_RE=1). Polarity is determined by the IS_RSTP_RE_INVERTED attribute. Tie to logic zero if not used. |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
Feature Control Attributes: Specifies how to use a given input data port (i.e., from general fabric, "DIRECT", or from another DSPCPLX, "CASCADE"). | ||||
A_INPUT_IM | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the A_IM port between direct input ("DIRECT") or the cascaded input from the previous DSP58 ("CASCADE"). |
A_INPUT_RE | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the A_RE port between direct input ("DIRECT") or the cascaded input from the previous DSP58 ("CASCADE"). |
B_INPUT_IM | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the B_IM port between parallel input ("DIRECT") or the cascaded input from the previous DSP48E2 ("CASCADE"). |
B_INPUT_RE | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the B_RE port between parallel input ("DIRECT") or the cascaded input from the previous DSP48E2 ("CASCADE"). |
RND_IM | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | All zeroes | 58-bit value used as the Rounding Constant into the WMUX of the IM side DSP slice. |
RND_RE | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | All zeroes | 58-bit value used as the Rounding Constant into the WMUX of the RE side DSP slice. |
Pattern Detector Attributes: Pattern Detection Configuration/Specification. | ||||
AUTORESET_PATDET_IM | STRING | "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" | "NO_RESET" | Automatically resets the P_IM Register (accumulated value or
counter value) on the next clock cycle, if a pattern detect event
has occurred on this clock cycle. The "RESET_MATCH" and
"RESET_NOT_MATCH" settings distinguish between whether
the DSP58 should cause an auto reset of the P Register
on the next cycle:
|
AUTORESET_PATDET_RE | STRING | "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" | "NO_RESET" | Automatically resets the P_RE Register (accumulated value or
counter value) on the next clock cycle, if a pattern detect event
has occurred on this clock cycle. The "RESET_MATCH" and
"RESET_NOT_MATCH" settings distinguish between whether
the DSP58 should cause an auto reset of the P Register
on the next cycle:
|
AUTORESET_PRIORITY_IM | STRING | "RESET", "CEP" | "RESET" | When using the AUTORESET_PATDET_IM feature, defines priority of AUTORESET_IM versus clock enable (CEP). |
AUTORESET_PRIORITY_RE | STRING | "RESET", "CEP" | "RESET" | When using the AUTORESET_PATDET_RE feature, defines priority of AUTORESET_RE versus clock enable (CEP). |
MASK_IM | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | 58'h0ffffffffffffff | This 58-bit value is used to mask out certain bits during a
pattern detection.
|
MASK_RE | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | 58'h0ffffffffffffff | This 58-bit value is used to mask out certain bits during a
pattern detection.
|
PATTERN_IM | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | All zeroes | This 58-bit value is used in the pattern detector. |
PATTERN_RE | HEX | %linebreak%%58'h000000000000000 to %linebreak%%58'h3ffffffffffffff | All zeroes | This 58-bit value is used in the pattern detector. |
SEL_MASK_IM | STRING | "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" | "MASK" | Selects the mask to be used for the pattern detector. The C_IM and MASK_IM settings are for standard uses of the pattern detector (counter, overflow detection, etc.). ROUNDING_MODE1 (C-bar left shifted by 1) and ROUNDING_MODE2 (C-bar left shifted by 2) select special masks based off of the optionally registered C_IM port. These rounding modes can be used to implement convergent rounding in the DSPCPLX using the pattern detector. |
SEL_MASK_RE | STRING | "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" | "MASK" | Selects the mask to be used for the pattern detector. The C_RE and MASK_RE settings are for standard uses of the pattern detector (counter, overflow detection, etc.). ROUNDING_MODE1 (C-bar left shifted by 1) and ROUNDING_MODE2 (C-bar left shifted by 2) select special masks based off of the optionally registered C port. These rounding modes can be used to implement convergent rounding in the DSPCPLX using the pattern detector. |
SEL_PATTERN_IM | STRING | "PATTERN", "C" | "PATTERN" | Selects the input source for the pattern field. The input source can be a 58-bit dynamic C_IM input or a 58-bit static PATTERN attribute field. |
SEL_PATTERN_RE | STRING | "PATTERN", "C" | "PATTERN" | Selects the input source for the pattern field. The input source can be a 58-bit dynamic C_RE input or a 58-bit static PATTERN_RE attribute field. |
USE_PATTERN_DETECT_IM | STRING | "NO_PATDET", "PATDET" | "NO_PATDET" | Selects whether the pattern detector and related features are used ("PATDET") or not used ("NO_PATDET"). This attribute is used for speed specification and Simulation Model purposes only. |
USE_PATTERN_DETECT_RE | STRING | "NO_PATDET", "PATDET" | "NO_PATDET" | Selects whether the pattern detector and related features are used ("PATDET") or not used ("NO_PATDET"). This attribute is used for speed specification and Simulation Model purposes only. |
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins for this component to change the active polarity of the pin function. When set to 1 on a clock pin (CLK), this component clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value specifies which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity. | ||||
IS_ALUMODE_IM_INVERTED | BINARY | 4'b0000 to 4'b1111 | 4'b0000 | Specifies whether or not to use the optional inverter on the individual ALUMODE_IM pins of this component. The default 4'b0000 indicates that all bits of the ALUMODE_IM bus are not inverted. Each bit controls its respective bit of the ALUMODE_IM bus. |
IS_ALUMODE_RE_INVERTED | BINARY | 4'b0000 to 4'b1111 | 4'b0000 | Specifies whether or not to use the optional inverter on the individual ALUMODE_RE pins of this component. The default 4'b0000 indicates that all bits of the ALUMODE_RE bus are not inverted. Each bit controls its respective bit of the ALUMODE_RE bus. |
IS_ASYNC_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the ASYNC_RST pin of this component. The default 1'b0 indicates that ASYNC_RST is not inverted. |
IS_CARRYIN_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CARRYIN_IM pin of this component. The default 1'b0 indicates that CARRYIN_IM is not inverted. |
IS_CARRYIN_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CARRYIN_RE pin of this component. The default 1'b0 indicates that CARRYIN_RE is not inverted. |
IS_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLK pin of this component. The default 1'b0 indicates that CLK is not inverted. |
IS_CONJUGATE_A_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CONJUGATE_A pin of this component. The default 1'b0 indicates that CONJUGATE_A_ is not inverted. |
IS_CONJUGATE_B_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CONJUGATE_B pin of this component. The default 1'b0 indicates that CONJUGATE_B is not inverted. |
IS_OPMODE_IM_INVERTED | BINARY | 9'b000000000 to 9'b111111111 | 9'b000000000 | Specifies whether or not to use the optional inversions on the individual OPMODE_IM pins of this component. The default 9'b000000000 indicates that all bits of the OPMODE_IM bus are not inverted. Each bit controls its respective bit of the OPMODE_IM bus. |
IS_OPMODE_RE_INVERTED | BINARY | 9'b000000000 to 9'b111111111 | 9'b000000000 | Specifies whether or not to use the optional inversions on the individual OPMODE_RE pins of this component. The default 9'b000000000 indicates that all bits of the OPMODE_RE bus are not inverted. Each bit controls its respective bit of the OPMODE_RE bus. |
IS_RSTAD_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTAD pin of this component. The default 1'b0 indicates that RSTAD is not inverted. |
IS_RSTA_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTA_IM pin of this component. The default 1'b0 indicates that RSTA_IM is not inverted. |
IS_RSTALLCARRYIN_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALLCARRYIN_IM pin of this component. The default 1'b0 indicates that RSTALLCARRYIN_IM is not inverted. |
IS_RSTALLCARRYIN_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALLCARRYIN_RE pin of this component. The default 1'b0 indicates that RSTALLCARRYIN_RE is not inverted. |
IS_RSTALUMODE_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALUMODE_IM pin of this component. The default 1'b0 indicates that RSTALUMODE_IM is not inverted. |
IS_RSTALUMODE_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALUMODE_RE pin of this component. The default 1'b0 indicates that RSTALUMODE_RE is not inverted. |
IS_RSTA_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTA_RE pin of this component. The default 1'b0 indicates that RSTA_RE is not inverted. |
IS_RSTB_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTB_IM pin of this component. The default 1'b0 indicates that RSTB_IM is not inverted. |
IS_RSTB_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTB_RE pin of this component. The default 1'b0 indicates that RSTB_RE is not inverted. |
IS_RSTC_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTC_IM pin of this component. The default 1'b0 indicates that RSTC_IM is not inverted. |
IS_RSTCONJUGATE_A_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTCONJUGATE_A pin of this component. The default 1'b0 indicates that RSTCONJUGATE_A is not inverted. |
IS_RSTCONJUGATE_B_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTCONJUGATE_B pin of this component. The default 1'b0 indicates that RSTCONJUGATE_B is not inverted. |
IS_RSTC_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTC_RE pin of this component. The default 1'b0 indicates that RSTC_RE is not inverted. |
IS_RSTCTRL_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTCTRL_IM pin of this component. The default 1'b0 indicates that RSTCTRL_IM is not inverted. |
IS_RSTCTRL_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTCTRL_RE pin of this component. The default 1'b0 indicates that RSTCTRL_RE is not inverted. |
IS_RSTM_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTM_IM pin of this component. The default 1'b0 indicates that RSTM_IM is not inverted. |
IS_RSTM_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTM_RE pin of this component. The default 1'b0 indicates that RSTM_RE is not inverted. |
IS_RSTP_IM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTP_IM pin of this component. The default 1'b0 indicates that RSTP_IM is not inverted. |
IS_RSTP_RE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTP_RE pin of this component. The default 1'b0 indicates that RSTP_RE is not inverted. |
Register Control Attributes: Pipeline Register Configuration/Specification | ||||
ACASCREG_IM | DECIMAL | 1, 0, 2 | 1 | In conjunction with AREG_IM, selects the number of A_IM input
registers on the A_IM cascade path, ACOUT_IM. This attribute must be
equal to or one less than the AREG_IM value:
|
ACASCREG_RE | DECIMAL | 1, 0, 2 | 1 | In conjunction with AREG_RE, selects the number of A_RE input
registers on the A cascade path, ACOUT_RE. This attribute must be
equal to or one less than the AREG_RE value:
|
ADREG | DECIMAL | 1, 0 | 1 | Selects the number of AD pipeline registers after the pre-adder. Applies to both real and imaginary DSP slices. |
ALUMODEREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of ALUMODE_IM input registers. |
ALUMODEREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of ALUMODE_RE input registers. |
AREG_IM | DECIMAL | 2, 0, 1 | 2 | Selects the number of A_IM input pipeline registers. If A_IM port is not in use, set to 1. |
AREG_RE | DECIMAL | 2, 0, 1 | 2 | Selects the number of A_RE input pipeline registers. If A_RE port is not in use, set to 1. |
BCASCREG_IM | DECIMAL | 1, 0, 2 | 1 | In conjunction with BREG_IM, selects the number of B_IM input
registers on the B_IM cascade path, BCOUT_IM. This attribute must be
equal to or one less than the BREG_IM value:
|
BCASCREG_RE | DECIMAL | 1, 0, 2 | 1 | In conjunction with BREG_RE, selects the number of B_RE input
registers on the B_RE cascade path, BCOUT_RE. This attribute must be
equal to or one less than the BREG_RE value:
|
BREG_IM | DECIMAL | 2, 0, 1 | 2 | Selects the number of B_IM input registers. If B_IM port is not in use, set to 1. |
BREG_RE | DECIMAL | 2, 0, 1 | 2 | Selects the number of B_RE input registers. If B_RE port is not in use, set to 1. |
CARRYINREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of CARRYIN_IM input registers. |
CARRYINREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of CARRYIN_RE input registers. |
CARRYINSELREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of CARRYINSEL_IM input registers. |
CARRYINSELREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of CARRYINSEL_RE input registers. |
CONJUGATEREG_A | DECIMAL | 1, 0 | 1 | Enable pipeline register for CONJUGATE_A. |
CONJUGATEREG_B | DECIMAL | 1, 0 | 1 | Enable pipeline register for CONJUGATE_B. |
CREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of C_IM input registers. If C_IM port is not in use, set to 1. |
CREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of C_RE input registers. If C_RE port is not in use, set to 1. |
MREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of multiplier output (M_IM) pipeline register stages. |
MREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of multiplier output (M_RE) pipeline register stages. |
OPMODEREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of OPMODE_IM input registers. |
OPMODEREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of OPMODE_RE input registers. |
PREG_IM | DECIMAL | 1, 0 | 1 | Selects the number of P output registers. The registered outputs will include CARRYOUT_IM, CARRYCASCOUT_IM, MULTSIGNOUT_IM, PATTERNB_DETECT_IM, PATTERN_DETECT_IM, and PCOUT_IM. |
PREG_RE | DECIMAL | 1, 0 | 1 | Selects the number of P output registers. The registered outputs will include CARRYOUT_RE, CARRYCASCOUT_RE, MULTSIGNOUT_RE, PATTERNB_DETECT_RE, PATTERN_DETECT_RE, and PCOUT_RE. |
RESET_MODE | STRING | "SYNC", "ASYNC" | "SYNC" | Selects if the enabled registers in the DSP are reset by their register specific synchronous resets (SYNC) or the common ASYNC_RST (ASYNC). |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DSPCPLX: 18 x 18 + 58 complex multiply accumulate block
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
DSPCPLX_inst : DSPCPLX
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT_IM => "DIRECT", -- Selects A_IM input source, "DIRECT" (A_IM port) or "CASCADE"
-- (ACIN_IM port)
A_INPUT_RE => "DIRECT", -- Selects A_RE input source, "DIRECT" (A_RE port) or "CASCADE"
-- (ACIN_RE port)
B_INPUT_IM => "DIRECT", -- Selects B_IM input source, "DIRECT" (B_IM port) or "CASCADE"
-- (BCIN_IM port)
B_INPUT_RE => "DIRECT", -- Selects B_RE input source, "DIRECT" (B_RE port) or "CASCADE"
-- (BCIN_RE port)
RND_IM => X"000000000000000", -- Rounding Constant
RND_RE => X"000000000000000", -- Rounding Constant
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET_IM => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH
AUTORESET_PATDET_RE => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH
AUTORESET_PRIORITY_IM => "RESET", -- Priority of AUTORESET_IM vs. CEP (CEP, RESET).
AUTORESET_PRIORITY_RE => "RESET", -- Priority of AUTORESET_RE vs. CEP (CEP, RESET).
MASK_IM => X"0ffffffffffffff", -- 58-bit mask value for pattern detect (1=ignore)
MASK_RE => X"0ffffffffffffff", -- 58-bit mask value for pattern detect (1=ignore)
PATTERN_IM => X"000000000000000", -- 58-bit pattern match for pattern detect
PATTERN_RE => X"000000000000000", -- 58-bit pattern match for pattern detect
SEL_MASK_IM => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
SEL_MASK_RE => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
SEL_PATTERN_IM => "PATTERN", -- Select pattern value (C, PATTERN)
SEL_PATTERN_RE => "PATTERN", -- Select pattern value (C, PATTERN)
USE_PATTERN_DETECT_IM => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET)
USE_PATTERN_DETECT_RE => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET)
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_ALUMODE_IM_INVERTED => "0000", -- Optional inversion for ALUMODE_IM
IS_ALUMODE_RE_INVERTED => "0000", -- Optional inversion for ALUMODE_RE
IS_CARRYIN_IM_INVERTED => '0', -- Optional inversion for CARRYIN_IM
IS_CARRYIN_RE_INVERTED => '0', -- Optional inversion for CARRYIN_RE
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_CONJUGATE_A_INVERTED => '0', -- Optional inversion for CONJUGATE_A
IS_CONJUGATE_B_INVERTED => '0', -- Optional inversion for CONJUGATE_B
IS_OPMODE_IM_INVERTED => "000000000", -- Optional inversion for OPMODE_IM
IS_OPMODE_RE_INVERTED => "000000000", -- Optional inversion for OPMODE_RE
IS_RSTAD_INVERTED => '0', -- Optional inversion for RSTAD
IS_RSTALLCARRYIN_IM_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN_IM
IS_RSTALLCARRYIN_RE_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN_RE
IS_RSTALUMODE_IM_INVERTED => '0', -- Optional inversion for RSTALUMODE_IM
IS_RSTALUMODE_RE_INVERTED => '0', -- Optional inversion for RSTALUMODE_RE
IS_RSTA_IM_INVERTED => '0', -- Optional inversion for RSTA_IM
IS_RSTA_RE_INVERTED => '0', -- Optional inversion for RSTA_RE
IS_RSTB_IM_INVERTED => '0', -- Optional inversion for RSTB_IM
IS_RSTB_RE_INVERTED => '0', -- Optional inversion for RSTB_RE
IS_RSTCONJUGATE_A_INVERTED => '0', -- Optional inversion for RSTCONJUGATE_A
IS_RSTCONJUGATE_B_INVERTED => '0', -- Optional inversion for RSTCONJUGATE_B
IS_RSTCTRL_IM_INVERTED => '0', -- Optional inversion for RSTCTRL_IM
IS_RSTCTRL_RE_INVERTED => '0', -- Optional inversion for RSTCTRL_RE
IS_RSTC_IM_INVERTED => '0', -- Optional inversion for RSTC_IM
IS_RSTC_RE_INVERTED => '0', -- Optional inversion for RSTC_RE
IS_RSTM_IM_INVERTED => '0', -- Optional inversion for RSTM_IM
IS_RSTM_RE_INVERTED => '0', -- Optional inversion for RSTM_RE
IS_RSTP_IM_INVERTED => '0', -- Optional inversion for RSTP_IM
IS_RSTP_RE_INVERTED => '0', -- Optional inversion for RSTP_RE
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG_IM => 1, -- Number of pipeline stages between A_IM/ACIN_IM and ACOUT_IM
-- (0-2)
ACASCREG_RE => 1, -- Number of pipeline stages between A_RE/ACIN_RE and ACOUT_RE
-- (0-2)
ADREG => 1, -- Pipeline stages for pre-adder (0-1)
ALUMODEREG_IM => 1, -- Pipeline stages for ALUMODE_IM (0-1)
ALUMODEREG_RE => 1, -- Pipeline stages for ALUMODE_RE (0-1)
AREG_IM => 2, -- Pipeline stages for A_IM (0-2)
AREG_RE => 2, -- Pipeline stages for A_RE (0-2)
BCASCREG_IM => 1, -- Number of pipeline stages between B_IM/BCIN_IM and BCOUT_IM
-- (0-2)
BCASCREG_RE => 1, -- Number of pipeline stages between B_RE/BCIN_RE and BCOUT_RE
-- (0-2)
BREG_IM => 2, -- Pipeline stages for B_IM (0-2)
BREG_RE => 2, -- Pipeline stages for B_RE (0-2)
CARRYINREG_IM => 1, -- Pipeline stages for CARRYIN_IM (0-1)
CARRYINREG_RE => 1, -- Pipeline stages for CARRYIN_RE (0-1)
CARRYINSELREG_IM => 1, -- Pipeline stages for CARRYINSEL_IM (0-1)
CARRYINSELREG_RE => 1, -- Pipeline stages for CARRYINSEL_RE (0-1)
CONJUGATEREG_A => 1, -- Pipeline stages for CONJUGATE_A (0-1)
CONJUGATEREG_B => 1, -- Pipeline stages for CONJUGATE_B (0-1)
CREG_IM => 1, -- Pipeline stages for C_IM (0-1)
CREG_RE => 1, -- Pipeline stages for C_RE (0-1)
MREG_IM => 1, -- Multiplier pipeline stages (0-1)
MREG_RE => 1, -- Multiplier pipeline stages (0-1)
OPMODEREG_IM => 1, -- Pipeline stages for OPMODE_IM (0-1)
OPMODEREG_RE => 1, -- Pipeline stages for OPMODE_RE (0-1)
PREG_IM => 1, -- Number of pipeline stages for P_IM (0-1)
PREG_RE => 1, -- Number of pipeline stages for P_RE (0-1)
RESET_MODE => "SYNC" -- Selection of synchronous or asynchronous reset. (ASYNC, SYNC).
)
port map (
-- Cascade outputs: Cascade Ports
ACOUT_IM => ACOUT_IM, -- 18-bit output: A_IM port cascade
ACOUT_RE => ACOUT_RE, -- 18-bit output: A_RE port cascade
BCOUT_IM => BCOUT_IM, -- 18-bit output: B_IM cascade
BCOUT_RE => BCOUT_RE, -- 18-bit output: B_RE cascade
CARRYCASCOUT_IM => CARRYCASCOUT_IM, -- 1-bit output: Cascade carry
CARRYCASCOUT_RE => CARRYCASCOUT_RE, -- 1-bit output: Cascade carry
MULTSIGNOUT_IM => MULTSIGNOUT_IM, -- 1-bit output: Multiplier sign cascade
MULTSIGNOUT_RE => MULTSIGNOUT_RE, -- 1-bit output: Multiplier sign cascade
PCOUT_IM => PCOUT_IM, -- 58-bit output: Cascade output
PCOUT_RE => PCOUT_RE, -- 58-bit output: Cascade output
-- Control outputs: Control Inputs/Status Bits
OVERFLOW_IM => OVERFLOW_IM, -- 1-bit output: Overflow in imaginary add/acc
OVERFLOW_RE => OVERFLOW_RE, -- 1-bit output: Overflow in real add/acc
PATTERNBDETECT_IM => PATTERNBDETECT_IM, -- 1-bit output: Pattern bar detect
PATTERNBDETECT_RE => PATTERNBDETECT_RE, -- 1-bit output: Pattern bar detect
PATTERNDETECT_IM => PATTERNDETECT_IM, -- 1-bit output: Pattern detect
PATTERNDETECT_RE => PATTERNDETECT_RE, -- 1-bit output: Pattern detect
UNDERFLOW_IM => UNDERFLOW_IM, -- 1-bit output: Underflow in add/acc
UNDERFLOW_RE => UNDERFLOW_RE, -- 1-bit output: Underflow in add/acc
-- Data outputs: Data Ports
CARRYOUT_IM => CARRYOUT_IM, -- 1-bit output: Carry-out
CARRYOUT_RE => CARRYOUT_RE, -- 1-bit output: Carry-out
P_IM => P_IM, -- 58-bit output: Primary data
P_RE => P_RE, -- 58-bit output: Primary data
-- Cascade inputs: Cascade Ports
ACIN_IM => ACIN_IM, -- 18-bit input: A_IM cascade data
ACIN_RE => ACIN_RE, -- 18-bit input: A_RE cascade data
BCIN_IM => BCIN_IM, -- 18-bit input: B_IM cascade
BCIN_RE => BCIN_RE, -- 18-bit input: B_RE cascade
CARRYCASCIN_IM => CARRYCASCIN_IM, -- 1-bit input: Cascade carry
CARRYCASCIN_RE => CARRYCASCIN_RE, -- 1-bit input: Cascade carry
MULTSIGNIN_IM => MULTSIGNIN_IM, -- 1-bit input: Multiplier sign cascade
MULTSIGNIN_RE => MULTSIGNIN_RE, -- 1-bit input: Multiplier sign cascade
PCIN_IM => PCIN_IM, -- 58-bit input: P_IM cascade
PCIN_RE => PCIN_RE, -- 58-bit input: P_IM cascade
-- Control inputs: Control Inputs/Status Bits
ALUMODE_IM => ALUMODE_IM, -- 4-bit input: ALU_IM control
ALUMODE_RE => ALUMODE_RE, -- 4-bit input: ALU_RE control
CARRYINSEL_IM => CARRYINSEL_IM, -- 3-bit input: Carry select
CARRYINSEL_RE => CARRYINSEL_RE, -- 3-bit input: Carry select
CLK => CLK, -- 1-bit input: Clock
CONJUGATE_A => CONJUGATE_A, -- 1-bit input: Select signal for cconjugate of A.
CONJUGATE_B => CONJUGATE_B, -- 1-bit input: Select signal for conjugate of B.
OPMODE_IM => OPMODE_IM, -- 9-bit input: Operation mode
OPMODE_RE => OPMODE_RE, -- 9-bit input: Operation mode
-- Data inputs: Data Ports
A_IM => A_IM, -- 18-bit input: A_IM data
A_RE => A_RE, -- 18-bit input: A_RE data
B_IM => B_IM, -- 18-bit input: B_IM data
B_RE => B_RE, -- 18-bit input: B_RE data
CARRYIN_IM => CARRYIN_IM, -- 1-bit input: Carry-in
CARRYIN_RE => CARRYIN_RE, -- 1-bit input: Carry-in
C_IM => C_IM, -- 58-bit input: C_IM data
C_RE => C_RE, -- 58-bit input: C_RE data
-- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
ASYNC_RST => ASYNC_RST, -- 1-bit input: Asynchronous reset for all registers.
CEA1_IM => CEA1_IM, -- 1-bit input: Clock enable for 1st stage AREG_IM
CEA1_RE => CEA1_RE, -- 1-bit input: Clock enable for 1st stage AREG_RE
CEA2_IM => CEA2_IM, -- 1-bit input: Clock enable for 2nd stage AREG_IM
CEA2_RE => CEA2_RE, -- 1-bit input: Clock enable for 2nd stage AREG_RE
CEAD => CEAD, -- 1-bit input: Clock enable for ADREG
CEALUMODE_IM => CEALUMODE_IM, -- 1-bit input: Clock enable for ALUMODE_IM
CEALUMODE_RE => CEALUMODE_RE, -- 1-bit input: Clock enable for ALUMODE_RE
CEB1_IM => CEB1_IM, -- 1-bit input: Clock enable for 1st stage BREG_IM
CEB1_RE => CEB1_RE, -- 1-bit input: Clock enable for 1st stage BREG_RE
CEB2_IM => CEB2_IM, -- 1-bit input: Clock enable for 2nd stage BREG_IM
CEB2_RE => CEB2_RE, -- 1-bit input: Clock enable for 2nd stage BREG_RE
CECARRYIN_IM => CECARRYIN_IM, -- 1-bit input: Clock enable for CARRYINREG_IM
CECARRYIN_RE => CECARRYIN_RE, -- 1-bit input: Clock enable for CARRYINREG_RE
CECONJUGATE_A => CECONJUGATE_A, -- 1-bit input: Clock enable for CONJUGATE_A
CECONJUGATE_B => CECONJUGATE_B, -- 1-bit input: Clock enable for CONJUGATE_B
CECTRL_IM => CECTRL_IM, -- 1-bit input: Clock enable for OPMODEREG_IM and CARRYINSELREG_IM
CECTRL_RE => CECTRL_RE, -- 1-bit input: Clock enable for OPMODEREG_RE and CARRYINSELREG_RE
CEC_IM => CEC_IM, -- 1-bit input: Clock enable for CREG_IM
CEC_RE => CEC_RE, -- 1-bit input: Clock enable for CREG_RE
CEM_IM => CEM_IM, -- 1-bit input: Clock enable for MREG_IM
CEM_RE => CEM_RE, -- 1-bit input: Clock enable for MREG_RE
CEP_IM => CEP_IM, -- 1-bit input: Clock enable for PREG_IM
CEP_RE => CEP_RE, -- 1-bit input: Clock enable for PREG
RSTAD => RSTAD, -- 1-bit input: Reset for ADREG
RSTALLCARRYIN_IM => RSTALLCARRYIN_IM, -- 1-bit input: Reset for CARRYINREG_IM
RSTALLCARRYIN_RE => RSTALLCARRYIN_RE, -- 1-bit input: Reset for CARRYINREG_RE
RSTALUMODE_IM => RSTALUMODE_IM, -- 1-bit input: Reset for ALUMODEREG_IM
RSTALUMODE_RE => RSTALUMODE_RE, -- 1-bit input: Reset for ALUMODEREG_RE
RSTA_IM => RSTA_IM, -- 1-bit input: Reset for AREG_IM
RSTA_RE => RSTA_RE, -- 1-bit input: Reset for AREG_RE
RSTB_IM => RSTB_IM, -- 1-bit input: Reset for BREG_IM
RSTB_RE => RSTB_RE, -- 1-bit input: Reset for BREG_RE
RSTCONJUGATE_A => RSTCONJUGATE_A, -- 1-bit input: Reset for CONJUGATE_A
RSTCONJUGATE_B => RSTCONJUGATE_B, -- 1-bit input: Reset for CONJUGATE_B
RSTCTRL_IM => RSTCTRL_IM, -- 1-bit input: Reset for OPMODEREG_IM and CARRYINSELREG_IM
RSTCTRL_RE => RSTCTRL_RE, -- 1-bit input: Reset for OPMODEREG_RE and CARRYINSELREG_RE
RSTC_IM => RSTC_IM, -- 1-bit input: Reset for CREG_IM
RSTC_RE => RSTC_RE, -- 1-bit input: Reset for CREG_RE
RSTM_IM => RSTM_IM, -- 1-bit input: Reset for MREG_IM
RSTM_RE => RSTM_RE, -- 1-bit input: Reset for MREG_RE
RSTP_IM => RSTP_IM, -- 1-bit input: Reset for PREG_IM
RSTP_RE => RSTP_RE -- 1-bit input: Reset for PREG_RE
);
-- End of DSPCPLX_inst instantiation
Verilog Instantiation Template
// DSPCPLX: 18 x 18 + 58 complex multiply accumulate block
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
DSPCPLX #(
// Feature Control Attributes: Data Path Selection
.A_INPUT_IM("DIRECT"), // Selects A_IM input source, "DIRECT" (A_IM port) or "CASCADE"
// (ACIN_IM port)
.A_INPUT_RE("DIRECT"), // Selects A_RE input source, "DIRECT" (A_RE port) or "CASCADE"
// (ACIN_RE port)
.B_INPUT_IM("DIRECT"), // Selects B_IM input source, "DIRECT" (B_IM port) or "CASCADE"
// (BCIN_IM port)
.B_INPUT_RE("DIRECT"), // Selects B_RE input source, "DIRECT" (B_RE port) or "CASCADE"
// (BCIN_RE port)
.RND_IM(58'h000000000000000), // Rounding Constant
.RND_RE(58'h000000000000000), // Rounding Constant
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET_IM("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
.AUTORESET_PATDET_RE("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
.AUTORESET_PRIORITY_IM("RESET"), // Priority of AUTORESET_IM vs. CEP (CEP, RESET).
.AUTORESET_PRIORITY_RE("RESET"), // Priority of AUTORESET_RE vs. CEP (CEP, RESET).
.MASK_IM(58'h0ffffffffffffff), // 58-bit mask value for pattern detect (1=ignore)
.MASK_RE(58'h0ffffffffffffff), // 58-bit mask value for pattern detect (1=ignore)
.PATTERN_IM(58'h000000000000000), // 58-bit pattern match for pattern detect
.PATTERN_RE(58'h000000000000000), // 58-bit pattern match for pattern detect
.SEL_MASK_IM("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
.SEL_MASK_RE("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
.SEL_PATTERN_IM("PATTERN"), // Select pattern value (C, PATTERN)
.SEL_PATTERN_RE("PATTERN"), // Select pattern value (C, PATTERN)
.USE_PATTERN_DETECT_IM("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET)
.USE_PATTERN_DETECT_RE("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET)
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_ALUMODE_IM_INVERTED(4'b0000), // Optional inversion for ALUMODE_IM
.IS_ALUMODE_RE_INVERTED(4'b0000), // Optional inversion for ALUMODE_RE
.IS_CARRYIN_IM_INVERTED(1'b0), // Optional inversion for CARRYIN_IM
.IS_CARRYIN_RE_INVERTED(1'b0), // Optional inversion for CARRYIN_RE
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_CONJUGATE_A_INVERTED(1'b0), // Optional inversion for CONJUGATE_A
.IS_CONJUGATE_B_INVERTED(1'b0), // Optional inversion for CONJUGATE_B
.IS_OPMODE_IM_INVERTED(9'b000000000), // Optional inversion for OPMODE_IM
.IS_OPMODE_RE_INVERTED(9'b000000000), // Optional inversion for OPMODE_RE
.IS_RSTAD_INVERTED(1'b0), // Optional inversion for RSTAD
.IS_RSTALLCARRYIN_IM_INVERTED(1'b0), // Optional inversion for RSTALLCARRYIN_IM
.IS_RSTALLCARRYIN_RE_INVERTED(1'b0), // Optional inversion for RSTALLCARRYIN_RE
.IS_RSTALUMODE_IM_INVERTED(1'b0), // Optional inversion for RSTALUMODE_IM
.IS_RSTALUMODE_RE_INVERTED(1'b0), // Optional inversion for RSTALUMODE_RE
.IS_RSTA_IM_INVERTED(1'b0), // Optional inversion for RSTA_IM
.IS_RSTA_RE_INVERTED(1'b0), // Optional inversion for RSTA_RE
.IS_RSTB_IM_INVERTED(1'b0), // Optional inversion for RSTB_IM
.IS_RSTB_RE_INVERTED(1'b0), // Optional inversion for RSTB_RE
.IS_RSTCONJUGATE_A_INVERTED(1'b0), // Optional inversion for RSTCONJUGATE_A
.IS_RSTCONJUGATE_B_INVERTED(1'b0), // Optional inversion for RSTCONJUGATE_B
.IS_RSTCTRL_IM_INVERTED(1'b0), // Optional inversion for RSTCTRL_IM
.IS_RSTCTRL_RE_INVERTED(1'b0), // Optional inversion for RSTCTRL_RE
.IS_RSTC_IM_INVERTED(1'b0), // Optional inversion for RSTC_IM
.IS_RSTC_RE_INVERTED(1'b0), // Optional inversion for RSTC_RE
.IS_RSTM_IM_INVERTED(1'b0), // Optional inversion for RSTM_IM
.IS_RSTM_RE_INVERTED(1'b0), // Optional inversion for RSTM_RE
.IS_RSTP_IM_INVERTED(1'b0), // Optional inversion for RSTP_IM
.IS_RSTP_RE_INVERTED(1'b0), // Optional inversion for RSTP_RE
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG_IM(1), // Number of pipeline stages between A_IM/ACIN_IM and ACOUT_IM
// (0-2)
.ACASCREG_RE(1), // Number of pipeline stages between A_RE/ACIN_RE and ACOUT_RE
// (0-2)
.ADREG(1), // Pipeline stages for pre-adder (0-1)
.ALUMODEREG_IM(1), // Pipeline stages for ALUMODE_IM (0-1)
.ALUMODEREG_RE(1), // Pipeline stages for ALUMODE_RE (0-1)
.AREG_IM(2), // Pipeline stages for A_IM (0-2)
.AREG_RE(2), // Pipeline stages for A_RE (0-2)
.BCASCREG_IM(1), // Number of pipeline stages between B_IM/BCIN_IM and BCOUT_IM
// (0-2)
.BCASCREG_RE(1), // Number of pipeline stages between B_RE/BCIN_RE and BCOUT_RE
// (0-2)
.BREG_IM(2), // Pipeline stages for B_IM (0-2)
.BREG_RE(2), // Pipeline stages for B_RE (0-2)
.CARRYINREG_IM(1), // Pipeline stages for CARRYIN_IM (0-1)
.CARRYINREG_RE(1), // Pipeline stages for CARRYIN_RE (0-1)
.CARRYINSELREG_IM(1), // Pipeline stages for CARRYINSEL_IM (0-1)
.CARRYINSELREG_RE(1), // Pipeline stages for CARRYINSEL_RE (0-1)
.CONJUGATEREG_A(1), // Pipeline stages for CONJUGATE_A (0-1)
.CONJUGATEREG_B(1), // Pipeline stages for CONJUGATE_B (0-1)
.CREG_IM(1), // Pipeline stages for C_IM (0-1)
.CREG_RE(1), // Pipeline stages for C_RE (0-1)
.MREG_IM(1), // Multiplier pipeline stages (0-1)
.MREG_RE(1), // Multiplier pipeline stages (0-1)
.OPMODEREG_IM(1), // Pipeline stages for OPMODE_IM (0-1)
.OPMODEREG_RE(1), // Pipeline stages for OPMODE_RE (0-1)
.PREG_IM(1), // Number of pipeline stages for P_IM (0-1)
.PREG_RE(1), // Number of pipeline stages for P_RE (0-1)
.RESET_MODE("SYNC") // Selection of synchronous or asynchronous reset. (ASYNC, SYNC).
)
DSPCPLX_inst (
// Cascade outputs: Cascade Ports
.ACOUT_IM(ACOUT_IM), // 18-bit output: A_IM port cascade
.ACOUT_RE(ACOUT_RE), // 18-bit output: A_RE port cascade
.BCOUT_IM(BCOUT_IM), // 18-bit output: B_IM cascade
.BCOUT_RE(BCOUT_RE), // 18-bit output: B_RE cascade
.CARRYCASCOUT_IM(CARRYCASCOUT_IM), // 1-bit output: Cascade carry
.CARRYCASCOUT_RE(CARRYCASCOUT_RE), // 1-bit output: Cascade carry
.MULTSIGNOUT_IM(MULTSIGNOUT_IM), // 1-bit output: Multiplier sign cascade
.MULTSIGNOUT_RE(MULTSIGNOUT_RE), // 1-bit output: Multiplier sign cascade
.PCOUT_IM(PCOUT_IM), // 58-bit output: Cascade output
.PCOUT_RE(PCOUT_RE), // 58-bit output: Cascade output
// Control outputs: Control Inputs/Status Bits
.OVERFLOW_IM(OVERFLOW_IM), // 1-bit output: Overflow in imaginary add/acc
.OVERFLOW_RE(OVERFLOW_RE), // 1-bit output: Overflow in real add/acc
.PATTERNBDETECT_IM(PATTERNBDETECT_IM), // 1-bit output: Pattern bar detect
.PATTERNBDETECT_RE(PATTERNBDETECT_RE), // 1-bit output: Pattern bar detect
.PATTERNDETECT_IM(PATTERNDETECT_IM), // 1-bit output: Pattern detect
.PATTERNDETECT_RE(PATTERNDETECT_RE), // 1-bit output: Pattern detect
.UNDERFLOW_IM(UNDERFLOW_IM), // 1-bit output: Underflow in add/acc
.UNDERFLOW_RE(UNDERFLOW_RE), // 1-bit output: Underflow in add/acc
// Data outputs: Data Ports
.CARRYOUT_IM(CARRYOUT_IM), // 1-bit output: Carry-out
.CARRYOUT_RE(CARRYOUT_RE), // 1-bit output: Carry-out
.P_IM(P_IM), // 58-bit output: Primary data
.P_RE(P_RE), // 58-bit output: Primary data
// Cascade inputs: Cascade Ports
.ACIN_IM(ACIN_IM), // 18-bit input: A_IM cascade data
.ACIN_RE(ACIN_RE), // 18-bit input: A_RE cascade data
.BCIN_IM(BCIN_IM), // 18-bit input: B_IM cascade
.BCIN_RE(BCIN_RE), // 18-bit input: B_RE cascade
.CARRYCASCIN_IM(CARRYCASCIN_IM), // 1-bit input: Cascade carry
.CARRYCASCIN_RE(CARRYCASCIN_RE), // 1-bit input: Cascade carry
.MULTSIGNIN_IM(MULTSIGNIN_IM), // 1-bit input: Multiplier sign cascade
.MULTSIGNIN_RE(MULTSIGNIN_RE), // 1-bit input: Multiplier sign cascade
.PCIN_IM(PCIN_IM), // 58-bit input: P_IM cascade
.PCIN_RE(PCIN_RE), // 58-bit input: P_IM cascade
// Control inputs: Control Inputs/Status Bits
.ALUMODE_IM(ALUMODE_IM), // 4-bit input: ALU_IM control
.ALUMODE_RE(ALUMODE_RE), // 4-bit input: ALU_RE control
.CARRYINSEL_IM(CARRYINSEL_IM), // 3-bit input: Carry select
.CARRYINSEL_RE(CARRYINSEL_RE), // 3-bit input: Carry select
.CLK(CLK), // 1-bit input: Clock
.CONJUGATE_A(CONJUGATE_A), // 1-bit input: Select signal for cconjugate of A.
.CONJUGATE_B(CONJUGATE_B), // 1-bit input: Select signal for conjugate of B.
.OPMODE_IM(OPMODE_IM), // 9-bit input: Operation mode
.OPMODE_RE(OPMODE_RE), // 9-bit input: Operation mode
// Data inputs: Data Ports
.A_IM(A_IM), // 18-bit input: A_IM data
.A_RE(A_RE), // 18-bit input: A_RE data
.B_IM(B_IM), // 18-bit input: B_IM data
.B_RE(B_RE), // 18-bit input: B_RE data
.CARRYIN_IM(CARRYIN_IM), // 1-bit input: Carry-in
.CARRYIN_RE(CARRYIN_RE), // 1-bit input: Carry-in
.C_IM(C_IM), // 58-bit input: C_IM data
.C_RE(C_RE), // 58-bit input: C_RE data
// Reset/Clock Enable inputs: Reset/Clock Enable Inputs
.ASYNC_RST(ASYNC_RST), // 1-bit input: Asynchronous reset for all registers.
.CEA1_IM(CEA1_IM), // 1-bit input: Clock enable for 1st stage AREG_IM
.CEA1_RE(CEA1_RE), // 1-bit input: Clock enable for 1st stage AREG_RE
.CEA2_IM(CEA2_IM), // 1-bit input: Clock enable for 2nd stage AREG_IM
.CEA2_RE(CEA2_RE), // 1-bit input: Clock enable for 2nd stage AREG_RE
.CEAD(CEAD), // 1-bit input: Clock enable for ADREG
.CEALUMODE_IM(CEALUMODE_IM), // 1-bit input: Clock enable for ALUMODE_IM
.CEALUMODE_RE(CEALUMODE_RE), // 1-bit input: Clock enable for ALUMODE_RE
.CEB1_IM(CEB1_IM), // 1-bit input: Clock enable for 1st stage BREG_IM
.CEB1_RE(CEB1_RE), // 1-bit input: Clock enable for 1st stage BREG_RE
.CEB2_IM(CEB2_IM), // 1-bit input: Clock enable for 2nd stage BREG_IM
.CEB2_RE(CEB2_RE), // 1-bit input: Clock enable for 2nd stage BREG_RE
.CECARRYIN_IM(CECARRYIN_IM), // 1-bit input: Clock enable for CARRYINREG_IM
.CECARRYIN_RE(CECARRYIN_RE), // 1-bit input: Clock enable for CARRYINREG_RE
.CECONJUGATE_A(CECONJUGATE_A), // 1-bit input: Clock enable for CONJUGATE_A
.CECONJUGATE_B(CECONJUGATE_B), // 1-bit input: Clock enable for CONJUGATE_B
.CECTRL_IM(CECTRL_IM), // 1-bit input: Clock enable for OPMODEREG_IM and CARRYINSELREG_IM
.CECTRL_RE(CECTRL_RE), // 1-bit input: Clock enable for OPMODEREG_RE and CARRYINSELREG_RE
.CEC_IM(CEC_IM), // 1-bit input: Clock enable for CREG_IM
.CEC_RE(CEC_RE), // 1-bit input: Clock enable for CREG_RE
.CEM_IM(CEM_IM), // 1-bit input: Clock enable for MREG_IM
.CEM_RE(CEM_RE), // 1-bit input: Clock enable for MREG_RE
.CEP_IM(CEP_IM), // 1-bit input: Clock enable for PREG_IM
.CEP_RE(CEP_RE), // 1-bit input: Clock enable for PREG
.RSTAD(RSTAD), // 1-bit input: Reset for ADREG
.RSTALLCARRYIN_IM(RSTALLCARRYIN_IM), // 1-bit input: Reset for CARRYINREG_IM
.RSTALLCARRYIN_RE(RSTALLCARRYIN_RE), // 1-bit input: Reset for CARRYINREG_RE
.RSTALUMODE_IM(RSTALUMODE_IM), // 1-bit input: Reset for ALUMODEREG_IM
.RSTALUMODE_RE(RSTALUMODE_RE), // 1-bit input: Reset for ALUMODEREG_RE
.RSTA_IM(RSTA_IM), // 1-bit input: Reset for AREG_IM
.RSTA_RE(RSTA_RE), // 1-bit input: Reset for AREG_RE
.RSTB_IM(RSTB_IM), // 1-bit input: Reset for BREG_IM
.RSTB_RE(RSTB_RE), // 1-bit input: Reset for BREG_RE
.RSTCONJUGATE_A(RSTCONJUGATE_A), // 1-bit input: Reset for CONJUGATE_A
.RSTCONJUGATE_B(RSTCONJUGATE_B), // 1-bit input: Reset for CONJUGATE_B
.RSTCTRL_IM(RSTCTRL_IM), // 1-bit input: Reset for OPMODEREG_IM and CARRYINSELREG_IM
.RSTCTRL_RE(RSTCTRL_RE), // 1-bit input: Reset for OPMODEREG_RE and CARRYINSELREG_RE
.RSTC_IM(RSTC_IM), // 1-bit input: Reset for CREG_IM
.RSTC_RE(RSTC_RE), // 1-bit input: Reset for CREG_RE
.RSTM_IM(RSTM_IM), // 1-bit input: Reset for MREG_IM
.RSTM_RE(RSTM_RE), // 1-bit input: Reset for MREG_RE
.RSTP_IM(RSTP_IM), // 1-bit input: Reset for PREG_IM
.RSTP_RE(RSTP_RE) // 1-bit input: Reset for PREG_RE
);
// End of DSPCPLX_inst instantiation
Related Information
- Versal ACAP DSP Engine Architecture Manual (AM004)