Primitive: General Clock Buffer with Divide Function
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
Introduction
BUFGCE_DIV is a general clock buffer with an enable and divide function.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CE | Input | 1 | Buffer enable input. |
CLR | Input | 1 | Asynchronous clear function forcing the output value to zero. |
I | Input | 1 | Buffer input. |
O | Output | 1 | Buffer output. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
BUFGCE_DIVIDE | DECIMAL | 1, 2, 3, 4, 5, 6, 7, 8 | 1 | Divide value. |
SIM_DEVICE | STRING | "VERSAL_AI_CORE", "VERSAL_AI_CORE_ES1", "VERSAL_AI_CORE_ES2" | "ULTRASCALE" | Set the device version |
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions are to be used on specific pins for this component to change the active polarity of the pin function. When set to 1, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity. | ||||
IS_CE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CE pin of this component. |
IS_CLR_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLR pin of this component. |
IS_I_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the I pin of this component. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE_DIV: General Clock Buffer with Divide Function
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
BUFGCE_DIV_inst : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 1, -- 1-8
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_CE_INVERTED => '0', -- Optional inversion for CE
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
IS_I_INVERTED => '0', -- Optional inversion for I
SIM_DEVICE => "VERSAL_AI_CORE" -- VERSAL_AI_CORE, VERSAL_AI_CORE_ES1
)
port map (
O => O, -- 1-bit output: Buffer
CE => CE, -- 1-bit input: Buffer enable
CLR => CLR, -- 1-bit input: Asynchronous clear
I => I -- 1-bit input: Buffer
);
-- End of BUFGCE_DIV_inst instantiation
Verilog Instantiation Template
// BUFGCE_DIV: General Clock Buffer with Divide Function
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
BUFGCE_DIV #(
.BUFGCE_DIVIDE(1), // 1-8
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
.IS_I_INVERTED(1'b0), // Optional inversion for I
.SIM_DEVICE("VERSAL_AI_CORE") // VERSAL_AI_CORE, VERSAL_AI_CORE_ES1
)
BUFGCE_DIV_inst (
.O(O), // 1-bit output: Buffer
.CE(CE), // 1-bit input: Buffer enable
.CLR(CLR), // 1-bit input: Asynchronous clear
.I(I) // 1-bit input: Buffer
);
// End of BUFGCE_DIV_inst instantiation
Related Information
- Versal ACAP Clocking Resources Architecture Manual (AM003)