Primitive: XPIO PLL
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
Introduction
The XPLL is a mixed signal block design to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift, and duty cycle based on the same VCO frequency. The primary function of the XPLL is to support the clocking needs of Memory Interface IP and XPHY Logic.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLKFB1_DESKEW | Input | 1 | Secondary (feedback) clock input to the PD1 block for deskewing clock network delays. |
CLKFB2_DESKEW | Input | 1 | Secondary (feedback) clock input to the PD2 block for deskewing clock network delays. |
CLKIN | Input | 1 | Primary clock input |
CLKIN1_DESKEW | Input | 1 | Primary clock input to the PD1 block for deskewing clock network delays between two different CLKOUT networks. |
CLKIN2_DESKEW | Input | 1 | Primary clock input to the PD2 block for deskewing clock network delays between two different CLKOUT networks. |
CLKOUTPHY | Output | 1 | General clock output connected to XPHY Logic. |
CLKOUTPHY_CASC_IN | Input | 1 | XPLL CLKOUTPHY cascade input |
CLKOUTPHY_CASC_OUT | Output | 1 | XPLL CLKOUTPHY cascade output |
CLKOUTPHYEN | Input | 1 | Enable signal for CLKOUTPHY. |
CLKOUT0 | Output | 1 | CLKOUT0 output. |
CLKOUT1 | Output | 1 | CLKOUT1 output. |
CLKOUT2 | Output | 1 | CLKOUT2 output. |
CLKOUT3 | Output | 1 | CLKOUT3 output. |
DADDR<6:0> | Input | 7 | The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. |
DCLK | Input | 1 | The DCLK signal is the reference clock for the dynamic reconfiguration port |
DEN | Input | 1 | The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. |
DI<15:0> | Input | 16 | The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. |
DO<15:0> | Output | 16 | The dynamic reconfiguration output bus provides XPLL data output when using dynamic reconfiguration. |
DRDY | Output | 1 | The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the XPLLs dynamic reconfiguration feature. |
DWE | Input | 1 | The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. |
LOCKED | Output | 1 | The LOCKED signal indicates that all functions requiring a LOCKED signal for the XPLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB, LOCKED1_DESKEW, and LOCKED2_DESKEW if used. |
LOCKED_FB | Output | 1 | An output from the XPLL that indicates when the XPLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The XPLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The XPLL must be reset after LOCKED is deasserted. |
LOCKED1_DESKEW | Output | 1 | Indicates if the PD1 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits. |
LOCKED2_DESKEW | Output | 1 | Indicates if the PD2 circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits. |
PSCLK | Input | 1 | Phase shift clock. |
PSDONE | Output | 1 | Phase shift done. |
PSEN | Input | 1 | Phase shift enable. |
PSINCDEC | Input | 1 | Phase shift increment/decrement. |
PWRDWN | Input | 1 | Powers down instantiated but unused XPLLs. |
RIU_ADDR<7:0> | Input | 8 | Dedicated connection to the DDRMC_RIU Register Interface Unit Address. |
RIU_CLK | Input | 1 | Dedicated connection to the DDRMC_RIU Register Interface Unit Clock. |
RIU_NIBBLE_SEL | Input | 1 | Dedicated connection to the DDRMC_RIU Register Interface Unit Nibble Select. |
RIU_RD_DATA<15:0> | Output | 16 | Dedicated connection to the DDRMC_RIU Register Interface Unit Read Data. |
RIU_VALID | Output | 1 | Dedicated connection to the DDRMC_RIU Register Interface Unit Interface Valid. |
RIU_WR_DATA<15:0> | Input | 16 | Dedicated connection to the DDRMC_RIU Register Interface Unit Write Data. |
RIU_WR_EN | Input | 1 | Dedicated connection to the DDRMC_RIU register Interface Unit Write Enable. |
RST | Input | 1 | Asynchronous reset signal. The RST signal is an asynchronous reset for the XPLL. The XPLL synchronously re-enables itself when this signal is released (that is, XPLL re-enabled). A reset is required when the input clock conditions change (for example, frequency). |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
CLKFBOUT_MULT | DECIMAL | 4 to 43 | 42 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. |
CLKFBOUT_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the XPLL. |
CLKIN_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN1 in ns. |
CLKOUTPHY_CASCIN_EN | BINARY | 1'b0 to 1'b1 | 1'b0 | XPLL CLKOUTPHY cascade input enable |
CLKOUTPHY_CASCOUT_EN | BINARY | 1'b0 to 1'b1 | 1'b0 | XPLL CLKOUTPHY cascade output enable |
CLKOUT0_DIVIDE | DECIMAL | 2 to 128 | 2 | Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT0_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
CLKOUT0_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT0 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT0_DIVIDE) / 8 |
CLKOUT0_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 | CLKOUT0 counter variable fine phase shift or deskew select.
|
CLKOUT1_DIVIDE | DECIMAL | 2 to 128 | 2 | Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT1_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
CLKOUT1_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT1 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT1_DIVIDE) / 8 |
CLKOUT1_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 | CLKOUT0 counter variable fine phase shift or deskew select.
|
CLKOUT2_DIVIDE | DECIMAL | 2 to 128 | 2 | Specifies the amount to divide the CLKOUT2 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT2_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT2 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
CLKOUT2_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT2 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT2_DIVIDE) / 8 |
CLKOUT2_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 | CLKOUT2 counter variable fine phase shift or deskew select.
|
CLKOUT3_DIVIDE | DECIMAL | 2 to 128 | 2 | Specifies the amount to divide the CLKOUT3 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT3_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT3 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
CLKOUT3_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT3 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT3_DIVIDE) / 8 |
CLKOUT3_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 | CLKOUT3 counter variable fine phase shift or deskew select.
|
DESKEW_DELAY_EN1 | STRING | "FALSE", "TRUE" | "FALSE" | Set to TRUE to enable the optional programmable delay in the PD1 circuit. |
DESKEW_DELAY_EN2 | STRING | "FALSE", "TRUE" | "FALSE" | Set to TRUE to enable the optional programmable delay in the PD1 circuit. |
DESKEW_DELAY_PATH1 | STRING | "FALSE", "TRUE" | "FALSE" | Determines if the CLKIN1_DESKEW path or the CLKFB1_DESKEW path is selected for the optional programmable delay. TRUE = CLKIN1_DESKEW, FALSE = CLKFB1_DESKEW. |
DESKEW_DELAY_PATH2 | STRING | "FALSE", "TRUE" | "FALSE" | Determines if the CLKIN2_DESKEW path or the CLKFB2_DESKEW path is selected for the optional programmable delay. TRUE = CLKIN2_DESKEW, FALSE = CLKFB2_DESKEW. |
DESKEW_DELAY1 | DECIMAL | 0 to 63 | 0 | Value of the optional programmable delay in the PD1 circuit. |
DESKEW_DELAY2 | DECIMAL | 0 to 63 | 0 | Value of the optional programmable delay in the PD2 circuit. |
DESKEW_MUXIN_SEL | BINARY | 1'b0 to 1'b1 | 1'b0 | Deskew mux selection |
DESKEW2_MUXIN_SEL | BINARY | 1'b0 to 1'b1 | 1'b0 | Deskew mux selection |
DIVCLK_DIVIDE | DECIMAL | 1 to 12 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD. |
IS_CLKFB1_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFB1_DESKEW pin. |
IS_CLKFB2_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFB2_DESKEW pin. |
IS_CLKIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN pin. |
IS_CLKIN1_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN1_DESKEW pin. |
IS_CLKIN2_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN2_DESKEW pin. |
IS_PSEN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSEN pin. |
IS_PSINCDEC_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSINCDEC pin. |
IS_PWRDWN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PWRDWN pin. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
LOCK_WAIT | STRING | "FALSE", "TRUE" | "FALSE" | Wait during the configuration for the startup for the XPLL to lock. |
REF_JITTER | 3 significant digit FLOAT | 0.000 to 0.200 | 0.010 | Allows specification of the expected jitter on CLKIN to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the unit interval (UI) (the maximum peak to peak value) of the expected jitter on the input clock. |
SIM_ADJ_CLK0_CASCADE | STRING | "FALSE", "TRUE" | "FALSE" | Simulation only attribute to reduce CLKOUT0 skew due to missing route delay. Setting the value to TRUE reduce the CLKOUT0 skew in the XPLL cascade. |
XPLL_CONNECT_TO_NOCMC | STRING | "NONE", "DDR", "LP4" | "NONE" | Indicates if the XPLL is used to drive the DDRMC. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- XPLL: XPIO PLL
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
XPLL_inst : XPLL
generic map (
CLKFBOUT_MULT => 42, -- Multiply value for all CLKOUT, (4-43)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB
CLKIN_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
CLKOUT0_DIVIDE => 2, -- Divide amount for CLKOUT0 (2-128)
CLKOUT0_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT0
CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0
CLKOUT0_PHASE_CTRL => "00", -- CLKOUT0 fine phase shift or deskew select (0-11)
CLKOUT1_DIVIDE => 2, -- Divide amount for CLKOUT1 (2-128)
CLKOUT1_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT1
CLKOUT1_PHASE => 0.0, -- Phase offset for CLKOUT1
CLKOUT1_PHASE_CTRL => "00", -- CLKOUT1 fine phase shift or deskew select (0-11)
CLKOUT2_DIVIDE => 2, -- Divide amount for CLKOUT2 (2-128)
CLKOUT2_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT2
CLKOUT2_PHASE => 0.0, -- Phase offset for CLKOUT2
CLKOUT2_PHASE_CTRL => "00", -- CLKOUT2 fine phase shift or deskew select (0-11)
CLKOUT3_DIVIDE => 2, -- Divide amount for CLKOUT3 (2-128)
CLKOUT3_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT3
CLKOUT3_PHASE => 0.0, -- Phase offset for CLKOUT3
CLKOUT3_PHASE_CTRL => "00", -- CLKOUT3 fine phase shift or deskew select (0-11)
CLKOUTPHY_CASCIN_EN => '0', -- XPLL CLKOUTPHY cascade input enable
CLKOUTPHY_CASCOUT_EN => '0', -- XPLL CLKOUTPHY cascade output enable
DESKEW2_MUXIN_SEL => '0', -- Deskew mux selection
DESKEW_DELAY1 => 0, -- Deskew optional programmable delay
DESKEW_DELAY2 => 0, -- Deskew optional programmable delay
DESKEW_DELAY_EN1 => "FALSE", -- Enable deskew optional programmable delay
DESKEW_DELAY_EN2 => "FALSE", -- Enable deskew optional programmable delay
DESKEW_DELAY_PATH1 => "FALSE", -- Select CLKIN1_DESKEW (TRUE) or CLKFB1_DESKEW (FALSE)
DESKEW_DELAY_PATH2 => "FALSE", -- Select CLKIN2_DESKEW (TRUE) or CLKFB2_DESKEW (FALSE)
DESKEW_MUXIN_SEL => '0', -- Deskew mux selection
DIVCLK_DIVIDE => 1, -- Master division value
IS_CLKFB1_DESKEW_INVERTED => '0', -- Optional inversion for CLKFB1_DESKEW
IS_CLKFB2_DESKEW_INVERTED => '0', -- Optional inversion for CLKFB2_DESKEW
IS_CLKIN1_DESKEW_INVERTED => '0', -- Optional inversion for CLKIN1_DESKEW
IS_CLKIN2_DESKEW_INVERTED => '0', -- Optional inversion for CLKIN2_DESKEW
IS_CLKIN_INVERTED => '0', -- Optional inversion for CLKIN
IS_PSEN_INVERTED => '0', -- Optional inversion for PSEN
IS_PSINCDEC_INVERTED => '0', -- Optional inversion for PSINCDEC
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
LOCK_WAIT => "FALSE", -- Lock wait
REF_JITTER => 0.0, -- Reference input jitter in UI (0.000-0.200).
SIM_ADJ_CLK0_CASCADE => "FALSE",
XPLL_CONNECT_TO_NOCMC => "NONE" -- XPLL driving the DDRMC
)
port map (
CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
CLKOUTPHY => CLKOUTPHY, -- 1-bit output: XPHY Logic clock
CLKOUTPHY_CASC_OUT => CLKOUTPHY_CASC_OUT, -- 1-bit output: XPLL CLKOUTPHY cascade output
DO => DO, -- 16-bit output: DRP data output
DRDY => DRDY, -- 1-bit output: DRP ready
LOCKED => LOCKED, -- 1-bit output: LOCK
LOCKED1_DESKEW => LOCKED1_DESKEW, -- 1-bit output: LOCK DESKEW PD1
LOCKED2_DESKEW => LOCKED2_DESKEW, -- 1-bit output: LOCK DESKEW PD2
LOCKED_FB => LOCKED_FB, -- 1-bit output: LOCK FEEDBACK
PSDONE => PSDONE, -- 1-bit output: Phase shift done
CLKFB1_DESKEW => CLKFB1_DESKEW, -- 1-bit input: Secondary clock input to PD1
CLKFB2_DESKEW => CLKFB2_DESKEW, -- 1-bit input: Secondary clock input to PD2
CLKIN => CLKIN, -- 1-bit input: Primary clock
CLKIN1_DESKEW => CLKIN1_DESKEW, -- 1-bit input: Primary clock input to PD1
CLKIN2_DESKEW => CLKIN2_DESKEW, -- 1-bit input: Primary clock input to PD2
CLKOUTPHYEN => CLKOUTPHYEN, -- 1-bit input: CLKOUTPHY enable
CLKOUTPHY_CASC_IN => CLKOUTPHY_CASC_IN, -- 1-bit input: XPLL CLKOUTPHY cascade input
DADDR => DADDR, -- 7-bit input: DRP address
DCLK => DCLK, -- 1-bit input: DRP clock
DEN => DEN, -- 1-bit input: DRP enable
DI => DI, -- 16-bit input: DRP data input
DWE => DWE, -- 1-bit input: DRP write enable
PSCLK => PSCLK, -- 1-bit input: Phase shift clock
PSEN => PSEN, -- 1-bit input: Phase shift enable
PSINCDEC => PSINCDEC, -- 1-bit input: Phase shift increment/decrement
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => RST -- 1-bit input: Reset
);
-- End of XPLL_inst instantiation
Verilog Instantiation Template
// XPLL: XPIO PLL
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
XPLL #(
.CLKFBOUT_MULT(42), // Multiply value for all CLKOUT, (4-43)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(2), // Divide amount for CLKOUT0 (2-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT0_PHASE_CTRL(2'b00), // CLKOUT0 fine phase shift or deskew select (0-11)
.CLKOUT1_DIVIDE(2), // Divide amount for CLKOUT1 (2-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT1
.CLKOUT1_PHASE_CTRL(2'b00), // CLKOUT1 fine phase shift or deskew select (0-11)
.CLKOUT2_DIVIDE(2), // Divide amount for CLKOUT2 (2-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT2
.CLKOUT2_PHASE_CTRL(2'b00), // CLKOUT2 fine phase shift or deskew select (0-11)
.CLKOUT3_DIVIDE(2), // Divide amount for CLKOUT3 (2-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT3
.CLKOUT3_PHASE_CTRL(2'b00), // CLKOUT3 fine phase shift or deskew select (0-11)
.CLKOUTPHY_CASCIN_EN(1'b0), // XPLL CLKOUTPHY cascade input enable
.CLKOUTPHY_CASCOUT_EN(1'b0), // XPLL CLKOUTPHY cascade output enable
.DESKEW2_MUXIN_SEL(1'b0), // Deskew mux selection
.DESKEW_DELAY1(0), // Deskew optional programmable delay
.DESKEW_DELAY2(0), // Deskew optional programmable delay
.DESKEW_DELAY_EN1("FALSE"), // Enable deskew optional programmable delay
.DESKEW_DELAY_EN2("FALSE"), // Enable deskew optional programmable delay
.DESKEW_DELAY_PATH1("FALSE"), // Select CLKIN1_DESKEW (TRUE) or CLKFB1_DESKEW (FALSE)
.DESKEW_DELAY_PATH2("FALSE"), // Select CLKIN2_DESKEW (TRUE) or CLKFB2_DESKEW (FALSE)
.DESKEW_MUXIN_SEL(1'b0), // Deskew mux selection
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFB1_DESKEW_INVERTED(1'b0), // Optional inversion for CLKFB1_DESKEW
.IS_CLKFB2_DESKEW_INVERTED(1'b0), // Optional inversion for CLKFB2_DESKEW
.IS_CLKIN1_DESKEW_INVERTED(1'b0), // Optional inversion for CLKIN1_DESKEW
.IS_CLKIN2_DESKEW_INVERTED(1'b0), // Optional inversion for CLKIN2_DESKEW
.IS_CLKIN_INVERTED(1'b0), // Optional inversion for CLKIN
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.LOCK_WAIT("FALSE"), // Lock wait
.REF_JITTER(0.0), // Reference input jitter in UI (0.000-0.200).
.SIM_ADJ_CLK0_CASCADE("FALSE"),
.XPLL_CONNECT_TO_NOCMC("NONE") // XPLL driving the DDRMC
)
XPLL_inst (
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUTPHY(CLKOUTPHY), // 1-bit output: XPHY Logic clock
.CLKOUTPHY_CASC_OUT(CLKOUTPHY_CASC_OUT), // 1-bit output: XPLL CLKOUTPHY cascade output
.DO(DO), // 16-bit output: DRP data output
.DRDY(DRDY), // 1-bit output: DRP ready
.LOCKED(LOCKED), // 1-bit output: LOCK
.LOCKED1_DESKEW(LOCKED1_DESKEW), // 1-bit output: LOCK DESKEW PD1
.LOCKED2_DESKEW(LOCKED2_DESKEW), // 1-bit output: LOCK DESKEW PD2
.LOCKED_FB(LOCKED_FB), // 1-bit output: LOCK FEEDBACK
.PSDONE(PSDONE), // 1-bit output: Phase shift done
.CLKFB1_DESKEW(CLKFB1_DESKEW), // 1-bit input: Secondary clock input to PD1
.CLKFB2_DESKEW(CLKFB2_DESKEW), // 1-bit input: Secondary clock input to PD2
.CLKIN(CLKIN), // 1-bit input: Primary clock
.CLKIN1_DESKEW(CLKIN1_DESKEW), // 1-bit input: Primary clock input to PD1
.CLKIN2_DESKEW(CLKIN2_DESKEW), // 1-bit input: Primary clock input to PD2
.CLKOUTPHYEN(CLKOUTPHYEN), // 1-bit input: CLKOUTPHY enable
.CLKOUTPHY_CASC_IN(CLKOUTPHY_CASC_IN), // 1-bit input: XPLL CLKOUTPHY cascade input
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data input
.DWE(DWE), // 1-bit input: DRP write enable
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
// End of XPLL_inst instantiation
Related Information
- Versal ACAP Clocking Resources Architecture Manual (AM003)