Primitive: Global Clock Buffer driven by fabric interconnect
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
Introduction
This design element is a high-fanout buffer that connects high fanout signals such as sets/resets and clock enables from the fabric interconnect to the global routing resources.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Buffer input |
| O | Output | 1 | Buffer input |
Design Entry Method
| Instantiation | Yes |
| Inference | Yes |
| IP and IP Integrator Catalog | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFG_FABRIC: Global Clock Buffer driven by fabric interconnect
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
BUFG_FABRIC_inst : BUFG_FABRIC
port map (
O => O, -- 1-bit output: Buffer
I => I -- 1-bit input: Buffer
);
-- End of BUFG_FABRIC_inst instantiation
Verilog Instantiation Template
// BUFG_FABRIC: Global Clock Buffer driven by fabric interconnect
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
BUFG_FABRIC BUFG_FABRIC_inst (
.O(O), // 1-bit output: Buffer
.I(I) // 1-bit input: Buffer
);
// End of BUFG_FABRIC_inst instantiation
Related Information
- Versal ACAP Clocking Resources Architecture Manual (AM003)