Primitive: Gigabit Transceiver Buffer
- PRIMITIVE_GROUP: ADVANCED
- PRIMITIVE_SUBGROUP: GT
Introduction
IBUFDS_GTE5 is the gigabit transceiver input pad buffer component. The REFCLK signal should be routed to the dedicated reference clock input pins on the serial transceiver, and the user design should instantiate the IBUFDS_GTE5 primitive in the user design. See the Versal ACAP Transceivers Architecture Manual for more information on PCB layout requirements, including reference clock requirements.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CEB | Input | 1 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
I | Input | 1 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
IB | Input | 1 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
O | Output | 1 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
ODIV2 | Output | 1 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
REFCLK_EN_TX_PATH | BINARY | 1'b0 to 1'b1 | 1'b0 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
REFCLK_HROW_CK_SEL | DECIMAL | 0, 1, 2, 3 | 0 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
REFCLK_ICNTL_RX | DECIMAL | 0, 1, 2, 3 | 0 | Refer to the Versal ACAP Transceivers Architecture Manual for more information. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDS_GTE5: Gigabit Transceiver Buffer
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2
IBUFDS_GTE5_inst : IBUFDS_GTE5
generic map (
REFCLK_EN_TX_PATH => '0', -- Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
REFCLK_HROW_CK_SEL => 0, -- Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
REFCLK_ICNTL_RX => 0 -- Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
)
port map (
O => O, -- 1-bit output: Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
ODIV2 => ODIV2, -- 1-bit output: Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
CEB => CEB, -- 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
I => I, -- 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
IB => IB -- 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
-- information.
);
-- End of IBUFDS_GTE5_inst instantiation
Verilog Instantiation Template
// IBUFDS_GTE5: Gigabit Transceiver Buffer
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.2
IBUFDS_GTE5 #(
.REFCLK_EN_TX_PATH(1'b0), // Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.REFCLK_HROW_CK_SEL(0), // Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.REFCLK_ICNTL_RX(0) // Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
)
IBUFDS_GTE5_inst (
.O(O), // 1-bit output: Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.ODIV2(ODIV2), // 1-bit output: Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.CEB(CEB), // 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.I(I), // 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
.IB(IB) // 1-bit input: Refer to the Versal ACAP Transceivers Architecture Manual for more
// information.
);
// End of IBUFDS_GTE5_inst instantiation
Related Information
- Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)