PCIE40E5 - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: Integrated block for PCI Express.

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: PCIE

Introduction

The Integrated block for PCI Express is a hard macro primitive compliant with the PCIe specification. This block is designed to be integrated with GTs and device clocking resources using fabric interconnect.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog No

Related Information

  • Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)