MBUFGCE - 2021.2 English

Primitive: Multi-Output Global Clock Buffer with Enable

PRIMITIVE_GROUP: CLOCK
PRIMITIVE_SUBGROUP: BUFFER

Introduction

This design element is a Multi-Output Global Clock Buffer with a single-gated input. The multiple clock outputs are generated close to the leaf clock pins instead of at the Clock Management Tile, which reduces clock pessimism on synchronous clock domain crossing paths. The output clocks are generated based on the MODE attribute.

Port Descriptions

Port	Direction	Width	Function
CE	Input	1	Clock buffer active-High enable.
CLRB_LEAF	Input	1	Active low clear of BUFDIV_LEAF
I	Input	1	Buffer input.
O1	Output	1	I in PERFORMANCE MODE I*2 in POWER MODE
O2	Output	1	I/2 in PERFORMANCE MODE I in POWER MODE
O3	Output	1	I/4 in PERFORMANCE MODE I/2 in POWER MODE
O4	Output	1	I/8 in PERFORMANCE MODE I/4 in POWER MODE

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Recommended

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CE_TYPE	STRING	"SYNC", "ASYNC", "HARDSYNC"	"SYNC"	Sets the clock enable behavior where SYNC allows for glitchless transition while ASYNC allows immediate transition. The SYNC setting times the CE pin in the Vivado tools while the ASYNC setting ignores the timing arc. HARD_SYNC turns on an internal 3-stage synchronizer for maximum performance. However, that results in a latency of either three or four clock cycles.
IS_CE_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Programmable inversion on CE
IS_I_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Programmable inversion on I
MODE	STRING	"PERFORMANCE", "POWER"	"PERFORMANCE"	Sets the mode of operation that determines the output clock generation. For PERFORMANCE MODE, the outputs are generated as follows: O1 = I O2 = I/2 O3 = I/4 O4 = I/8 For POWER MODE, the outputs are generated as follows: O1 = I*2 O2 = I O3 = I/2 O4 = I/4

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- MBUFGCE: Multi-Output Global Clock Buffer with Enable
--          Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2

MBUFGCE_inst : MBUFGCE
generic map (
   CE_TYPE => "SYNC",     -- ASYNC, HARDSYNC, SYNC
   IS_CE_INVERTED => '0', -- Programmable inversion on CE
   IS_I_INVERTED => '0',  -- Programmable inversion on I
   MODE => "PERFORMANCE"  -- PERFORMANCE, POWER
)
port map (
   O1 => O1,               -- 1-bit output: Buffer
   O2 => O2,               -- 1-bit output: Buffer
   O3 => O3,               -- 1-bit output: Buffer
   O4 => O4,               -- 1-bit output: Buffer
   CE => CE,               -- 1-bit input: Buffer enable
   CLRB_LEAF => CLRB_LEAF, -- 1-bit input: Active low clear
   I => I                  -- 1-bit input: Buffer
);

-- End of MBUFGCE_inst instantiation

Verilog Instantiation Template


// MBUFGCE: Multi-Output Global Clock Buffer with Enable
//          Versal AI Core series
// Xilinx HDL Language Template, version 2021.2

MBUFGCE #(
   .CE_TYPE("SYNC"),      // ASYNC, HARDSYNC, SYNC
   .IS_CE_INVERTED(1'b0), // Programmable inversion on CE
   .IS_I_INVERTED(1'b0),  // Programmable inversion on I
   .MODE("PERFORMANCE")   // PERFORMANCE, POWER
)
MBUFGCE_inst (
   .O1(O1),               // 1-bit output: Buffer
   .O2(O2),               // 1-bit output: Buffer
   .O3(O3),               // 1-bit output: Buffer
   .O4(O4),               // 1-bit output: Buffer
   .CE(CE),               // 1-bit input: Buffer enable
   .CLRB_LEAF(CLRB_LEAF), // 1-bit input: Active low clear
   .I(I)                  // 1-bit input: Buffer
);

// End of MBUFGCE_inst instantiation

Related Information

Versal ACAP Clocking Resources Architecture Manual (AM003)