XCI Inferencing - 2021.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
Release Date
2021.1 English

In some cases, a user code might have commonly-used Xilinx IP instantiated within their RTL. The Reference RTL Module feature allows inferencing the XCI (.xci) files for IP embedded within the RTL code.

While a majority of the IP are supported for inferencing, there a few IP that are not supported to be inferenced within the RTL flow. The unsupported IP are, as follows:

  • Those with processor data
  • Those that support elaboration (HIP)
  • Those that support AppCore
  • HLS based
    • The IPDEF property ipcomp includes the string “xilinx_anylanguagehls”
  • Do not have RTL enabled
    • The IPDEF property design_tool_contexts does not include “HDL”
  • Hard-coded VLNV list:
    • mig_7series
    • selectio_wiz
    • microblaze_mcs
    • ddr*
    • zynq_ultra_ps_e
    • axi_crossbar
    • ibert_ultrascale_gth
    • ibert_ultrascale_gty
    • gtwizard
    • microblaze

If an IP from the above list happens to be instantiated within the RTL code, then the Add Module command will fail with the following error:

ERROR: [filemgmt 56-181] Reference '<targetName> contains sub-design file '<xciFile>'. This sub-design is not allowed in the reference due to following reason(s): The <vlnv> core does not support module reference.

As an example, the code snippet, shown in the following figure, shows that an ILA was instantiated within the RTL code.

Figure 1. ILA IP Instantiated in RTL

The ILA IP has been configured and added to the project, shown below:

Figure 2. ILA IP Configured and Added to Project

This RTL can then be added to the block design as an RTL module. It looks like the following figure.

Figure 3. RTL with ILA IP Instantiated as a Module Reference in BD