PLL Integer Divider Programming - 2020.2 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2020-11-24
Version
2020.2 English

To operate the VCU PLL, configure the VCU_SLCR. VCU_PLL_CFG register using the values in the following table. The following fields must be programmed.

  • VCU_SLCR.VCU_PLL_CFG[LOCK_DLY]
  • VCU_SLCR.VCU_PLL_CFG[LOCK_CNT]
  • VCU_SLCR.VCU_PLL_CFG[LFHF]
  • VCU_SLCR.VCU_PLL_CFG[CP]
  • VCU_SLCR.VCU_PLL_CFG[RES]

The FBDIV value (or the PLL feedback multiplier value, M) depends on the output VCO frequency (fvco). You must program VCU_SRCR.VCU_PLL_CFG based on the calculated FBDIV values in the following table.

Table 1. PLL Programming for Integer Feedback Divider Values
FBDIV CP RES LFHF LOCK_DLY LOCK_CNT
25 3 10 3 63 1000
26 3 10 3 63 1000
27 4 6 3 63 1000
28 4 6 3 63 1000
29 4 6 3 63 1000
30 4 6 3 63 1000
31 6 1 3 63 1000
32 6 1 3 63 1000
33 4 10 3 63 1000
34 5 6 3 63 1000
35 5 6 3 63 1000
36 5 6 3 63 1000
37 5 6 3 63 1000
38 5 6 3 63 975
39 3 12 3 63 950
40 3 12 3 63 925
41 3 12 3 63 900
42 3 12 3 63 875
43 3 12 3 63 850
44 3 12 3 63 850
45 3 12 3 63 825
46 3 12 3 63 800
47 3 12 3 63 775
48 3 12 3 63 775
49 3 12 3 63 750
50 3 12 3 63 750
51 3 2 3 63 725
52 3 2 3 63 700
53 3 2 3 63 700
54 3 2 3 63 675
55 3 2 3 63 675
56 3 2 3 63 650
57 3 2 3 63 650
58 3 2 3 63 625
59 3 2 3 63 625
60 3 2 3 63 625
61 3 2 3 63 600
62 3 2 3 63 600
63 3 2 3 63 600
64 3 2 3 63 600
65 3 2 3 63 600
66 3 2 3 63 600
67 3 2 3 63 600
68 3 2 3 63 600
69 3 2 3 63 600
70 3 2 3 63 600
71 3 2 3 63 600
72 3 2 3 63 600
73 3 2 3 63 600
74 3 2 3 63 600
75 3 2 3 63 600
76 3 2 3 63 600
77 3 2 3 63 600
78 3 2 3 63 600
79 3 2 3 63 600
80 3 2 3 63 600
81 3 2 3 63 600
82 3 2 3 63 600
83 4 2 3 63 600
84 4 2 3 63 600
85 4 2 3 63 600
86 4 2 3 63 600
87 4 2 3 63 600
88 4 2 3 63 600
89 4 2 3 63 600
90 4 2 3 63 600
91 4 2 3 63 600
92 4 2 3 63 600
93 4 2 3 63 600
94 4 2 3 63 600
95 4 2 3 63 600
96 4 2 3 63 600
97 4 2 3 63 600
98 4 2 3 63 600
99 4 2 3 63 600
100 4 2 3 63 600
101 4 2 3 63 600
102 4 2 3 63 600
103 5 2 3 63 600
104 5 2 3 63 600
105 5 2 3 63 600
106 5 2 3 63 600
107 3 4 3 63 600
108 3 4 3 63 600
109 3 4 3 63 600
110 3 4 3 63 600
111 3 4 3 63 600
112 3 4 3 63 600
113 3 4 3 63 600
114 3 4 3 63 600
115 3 4 3 63 600
116 3 4 3 63 600
117 3 4 3 63 600
118 3 4 3 63 600
119 3 4 3 63 600
120 3 4 3 63 600
121 3 4 3 63 600
122 3 4 3 63 600
123 3 4 3 63 600
124 3 4 3 63 600
125 3 4 3 63 600
Note: The range for FBDIV is based on what is supported in silicon. A minimum value of 25 is determined based on the minimum VCO frequency and the maximum input clock frequency. The applicable values for FBDIV are determined by the fVCO, VCO output frequency range. For VCU PLL, the range is 1500-3000 MHz. FBDIV should be determined based on the fVCO, required output frequency and the input clock frequency. For example, for a 27 MHz input frequency and a 666 MHz VCU operating frequency, the possible FBDIV value is 2664/27= 99. Also, the maximum value of FBDIV for 27 MHz will be 3000/27=111. Similarly, the minimum value of FBDIV for 60 MHz will be 1500/60=25.