|
Core
Specifics |
| Supported Device Family
1
|
Zynq®
UltraScale+™ MPSoC EV Devices |
| Supported User Interfaces |
AXI4
|
| Resources |
See Resource Utilization
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
Not Provided |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File
(XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation
3
|
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado® Design Suite
|
| Support |
| Release Notes and Known
Issues |
Master Answer Record:
66763
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
| Provided
by Xilinx at the Xilinx Support web page
|
- For a complete list of
supported devices, see the
Vivado®
IP catalog.
- For the supported versions of
the tools, see the Xilinx Design Tools:
Release Notes Guide.
- Behavioral simulations using only Verilog simulation
models are supported. Netlist (post-synthesis and
post-implementation) simulations are not supported.
|