Interfacing the Core with Zynq UltraScale+ MPSoC Devices - 2020.2 English - PG252

To integrate the VCU core into an IP integrator (IPI) block design, follow these steps:

1. Launch the Vivado IDE and create a new project.
   
   
2. Click Next on New Project wizard until you reach the Family Selection window.
3. Select a target device for the VCU core.
   
   
4. Click on the Project Settings window. Click Implementation.
   
   
5. In the Settings window, enable the Performance_Explore option by selecting Settings > Implementation > Options > Strategy: Performance_Explore See the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information.
6. Click Create Block Design.
7. Click Add IP and type VCU. The following IP appears.
   
   
8. Add Zynq UltraScale+ VCU to the block design.
9. Add Zynq UltraScale+ MPSoC IP to the block design as shown.
   
   
10. Configure Zynq UltraScale+ MPSoC to enable AXI slave interfaces, clocking, and PL-PS interrupt signal per your design requirements. Refer to the Zynq UltraScale+ MPSoC Processing System LogiCORE IP Product Guide (PG201) for configuration options of the Zynq UltraScale+ MPSoC IP.

    The following figure shows an example of configuring the PS-PL interface signals.

11. Select PL1 clock frequency as 300 MHz.
    
    
12. Enable IRQ0 [0-7] and HP0-3 ports.
    
    
13. Use connection automation to connect the S_AXI_LITE interface of VCU IP to the M_AXI_HPM0_LPD interface.
    
    
14. Connect the following interfaces manually:
    • Zynq UltraScale+ VCU.M_AXI_ENC1 to Zynq UltraScale+ MPSoC.S_AXI_HP1_FPD
    • Zynq UltraScale+ VCU.M_AXI_DEC0 to Zynq UltraScale+ MPSoC.S_AXI_HP0_FPD
    • Zynq UltraScale+ VCU.M_AXI_DEC1 to Zynq UltraScale+ MPSoC.S_AXI_HP3_FPD

    Note the selection of MPSoC.S_AXI_HP1_FPD, MPSoC.S_AXI_HP0_FPD, and MPSoC.S_AXI_HP3_FPD. These are non-coherent, high-performance DMA ports for large datasets. They support AXI FIFO QoS-400 traffic shaping. For each of these ports, there is an associated register set. The register addresses are needed for command line configuration of quality of service and issuing capability using the devmem command.

    The address and description of S_AXI_HP1_FPD can be found in Zynq UltraScale+ Device Register Reference (UG1087). The address is 0xFD390000. The register is used to configure QoS and the FIFO. It is part of the AFIFM Module. The AFIFM Module documentation provides relative addresses and values for fields defining traffic priority and maximum number of read or write commands.

    
    
    
15. Add the AXI Interconnect IP and set number of slave interfaces to 2 and master interface to 1 as shown in the following figure.
    
    
16. Perform the following connections manually:
    • Instantiate the processor system reset IP. A second reset block is needed for the pl_clk1 clock domain.
    • Connect the slowest sync clock to the pl_clk1 port.
    • Use the interconnect_aresetn port as the ARESETN input to the AXI Interconnect IP core.
    • Use peripheral_aresetn port as a reset input to the S00_ARESETN, S01_ARESETN, and M00_ARESETN ports as shown in the following figure.
      
      
    • Connect the ext_reset_n signal to the pl_resetn0 signal of Zynq UltraScale+ MPSoC.
    • Connect the vcu_host_interrupt to the pl_ps_irq port of Zynq UltraScale+ MPSoC IP.
17. Connect up the following clocks to the pl_clk1 output of Zynq UltraScale+ MPSoC core:
    • AXI Interconnect: aclk
    • AXI Interconnect: s00_aclk
    • AXI Interconnect: s01_aclk
    • AXI Interconnect: m01_aclk
    • VCU: m_axi_mcu_aclk
    • VCU: m_axi_enc_aclk
    • VCU: m_axi_dec_aclk
    • Zynq UltraScale+ MPSoC: saxihp0_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp1_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp2_fpd_aclk
    • Zynq UltraScale+ MPSoC: saxihp3_fpd_aclk
18. Connect saxihp0_fpd_aclk, saxihp1_fpd_aclk, saxihp2_fpd_aclk and saxihp3_fpd_aclk to pl_clk1 output of Zynq UltraScale+ MPSoC core.
19. Tie off the vcu_resetn signal of Zynq UltraScale+ MPSoC VCU to either AXI GPIO or ZynqMP GPIO (EMIO).
20. Make pll_ref_clk signal as external.
21. In the Address Editor tab, expand EncData address segment and auto assign the addresses. The following table shows an example address map.
    
    
22. Click on Validate Block Design to validate the connections.
    
    
23. Create a top-level Vivado wrapper by right-clicking on Block Design and selecting Create HDL Wrapper option as shown in the following figure.
    
    
24. Add constraints file to the project.
25. Add the constraints file (.xdc) from the board support package if available. If no constraints file is available, several settings must be changed from their default values to enable error-free bitstream generation. In the I/O ports window, for pll_ref_clk_0, the I/O Std must be changed from LVCMOS18 (Default) to LVCMOS18.

    And on the same row, the Fixed checkbox must be checked. This corresponds to an XDC file containing the following:

    • set_property IOSTANDARD LVCMOS18 [get_ports pll_ref_clk_0]
    • set_property PACKAGE_PIN AA2 [get_ports pll_ref_clk_0]
26. Click on the Run Synthesis, Run Implementation, or Generate Bitstream option.