The following figure shows how the IP is connected to VCU LogiCORE IP.
The following table shows the recommended port connection.
| VCU DDR4 Controller Port | Master Port | Priority |
|---|---|---|
| S_AXI_PORT0 | M_AXI_DEC0 (through AXI interconnect) | High |
| S_AXI_PORT1 | M_AXI_DEC1 (through AXI interconnect) | High |
| S_AXI_PORT2 | M_AXI_MCU (through AXI interconnect) | Low |
| S_AXI_PORT3 | M_AXI_HPM0/1 (through AXI interconnect) | Low |
| S_AXI_PORT4 | M00_AXI (Video mixer or frame buffer read master) | High |
I/O Planning
DDR4 SDRAM I/O pin planning is completed with the full design pin planning using the Vivado I/O pin planner. DDR4 SDRAM I/O pins can be selected through several Vivado I/O pin planner features including assignments using I/O Ports view, Package view, or Memory Bank/Byte Planner. Pin assignments can additionally be made through importing an XDC or modifying the existing XDC file.
These options are available for all DDR4 SDRAM designs and multiple DDR4 SDRAM IP instances can be completed in one setting. To learn more about the available Memory IP pin planning options, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).