MCU Register Overview - 2020.2 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2020-11-24
Version
2020.2 English

The following table lists the MCU registers. For additional information, see the Zynq UltraScale+ Device Register Reference (UG1087) .

Table 1. Encoder MCU Registers
Register Address Width Type Reset Value Description
MCU_RESET 0xA0009000 32 mixed 1 0x00000000 MCU Subsystem Reset
MCU_RESET_MODE 0xA0009004 32 mixed 1 0x00000001 MCU Reset Mode
MCU_STA 0xA0009008 32 mixed 1 0x00000000 MCU Status
MCU_WAKEUP 0xA000900C 32 mixed 1 0x00000000 MCU Wake-up
MCU_ADDR_OFFSET_IC0 0xA0009010 32 rw 0x00000000 MCU Instruction Cache Address Offset 0
MCU_ADDR_OFFSET_IC1 0xA0009014 32 rw 0x00000000 MCU Instruction Cache Address Offset 1
MCU_ADDR_OFFSET_DC0 0xA0009018 32 rw 0x00000000 MCU Data Cache Address Offset 0
MCU_ADDR_OFFSET_DC1 0xA000901C 32 rw 0x00000000 MCU Data Cache Address Offset 1
  1. Mixed registers are registers that have read only, write only, and read write bits grouped together.