Clocking and Reset Registers - 2020.2 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2020-11-24
Version
2020.2 English

The following table lists the clocking and reset registers.

Table 1. Clocking and Reset Registers
Register Address Width Type Reset Value Description
CRL_WPROT 0xA0040020 1 rw 0x00000000 CRL SLCR Write protection register
VCU_PLL_CTRL 0xA0040024 32 mixed 1 0x0000510F PLL Basic Control
VCU_PLL_CFG 0xA0040028 32 mixed 1 0x00000000 Helper data
PLL_STATUS 0xA0040060 32 mixed 1 0x00000008 Status of the PLLs
  1. Mixed registers are registers that have read only, write only, and read write bits grouped together.