Instantiating the IP - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID

PG314

Release Date

2021-02-05

Version

1.3 English

The Timer Syncer IP is a hidden IP and therefore you need to use the following Tcl commands for instantiating the IP:

```
create_bd_design "design_1"
```
```
set_param bd.skipSupportedIPCheck true
```

set ptp_1588_timer_syncer_0 [ create_bd_cell -type ip -vlnv 
xilinx.com:ip:ptp_1588_timer_syncer ptp_1588_timer_syncer_0 ]

set_property -dict [ list \
CONFIG.CORE_MODE {Timer_Syncer} \
CONFIG.ENABLE_EXT_TOD_BUS {1} \
CONFIG.NUM_PORTS {1} \
CONFIG.TIMER_FORMAT {Time_of_Day} \
CONFIG.TS_CLK_PERIOD {4.0} \
] $ptp_1588_timer_syncer_0

Note: TS_CLK_PERIOD : 4.0 (250MHz)

```
startgroup
```

make_bd_pins_external  [get_bd_cells ptp_1588_timer_syncer_0] -quiet

make_bd_intf_pins_external  [get_bd_cells ptp_1588_timer_syncer_0] -quiet

```
endgroup
```
```
assign_bd_address
```
```
validate_bd_design
```
```
save_bd_design
```
```
create the HDL wrapper
```
```
update_compile_order -fileset sources_1
```
Now instantiate the design_1_wrapper() in the design and connect appropriately with the Ethernet IP and the AXI4Lite interface.
Note: When the 1588 checkbox is enabled in MRMAC GUI, this Timer syncer IP automatically generates and appropriately connects in the example design. For reference, you can generate the Example design of the MRMAC IP core.