The GT Quad Operating Modes table lists the supported MRMAC GT Quad interface clock frequency for each
operating mode. All GT Quad lane interfaces for a port operating in a multi-lane operating
modes have the same configuration. The ctl_serdes_width[2]
bit selects the GT Quad interface to operate in narrow interface width or wider x2 GT Quad
interface width.
The following table shows a list of MRMAC-supported interface options for FEC-only mode, including the associated data rates, datapath width, and clock frequency.
| Operating Mode | RS (528,514) | RS (544,514) | FEC-Only Rate (Gb/s) | FEC-Only Interface Data Width (Bits) | FEC-Only Interface Clock (MHz) | FEC-Only Logic Internal Clock (MHz) |
|---|---|---|---|---|---|---|
| 25.78125 FEC-only | ✓ | – | 25.78125 | 80 | 322.2556 | 644.5313 |
| 51.5625G FEC-only | ✓ | – | 51.5625 | 160 | 322.2556 | 644.5313 |
| 53.125G FEC-only | – | ✓ | 53.125 | 160 | 322.0312 | 644.0625 |
| 56.42G FEC-only | – | ✓ | 56.42 | 160 | 352.625 | 705.25 |
| 103.125 FEC-only | ✓ | – | 103.125 | 320 | 322.2556 | 644.5313 |
| 106.125G FEC-only | – | ✓ | 106.25 | 320 | 332.0312 | 664.0625 |
| 112.84G FEC-only | – | ✓ | 112.84 | 320 | 352.625 | 705.25 |
When configured in x2 width mode, the GT Quad interface from the lane is
clocked by rx_alt_serdes_clk[n] and tx_alt_serdes_clk[n]. The rx_serdes_clk[n]
connects to a GT Quad transceiver generated clock whose frequency is x2 rx_alt_serdes_clk[n]. The tx_core_clk[m] is driven by the GT Quad generated x2 tx_alt_serdes_clk[n] clock (where n is the lane number and m is the port
number).
A full pin description of the GT Quad interface is provided in the later Transceiver Interface section and the GT interface clocking examples are in the Clocking Use Cases section.