When the TX AXI4-Stream interface is
configured in the independent clock mode (ctl_tx_axis_cfg[0] =
1) field of the MODE_REG register, the AXI4-Stream output tx_axis_tskid_en_<N>
becomes an almost full signal for the MRMAC ingress data FIFO.
The user logic can take advantage of this signal to simplify its egress data
pipeline. The tx_axis_tskid_en signal can be viewed as an advanced warning
that the AXI4-Stream TX interface is about to deassert its
tx_axis_tready signal (which would mean the user logic would have to
stall its pipeline on-the-fly and hold the data present on the bus until
tready is re-asserted). The skid feature allows the user logic to
deassert the tx_axis_tvalid signal within 0 to 3 cycles after the assertion
of tx_axis_tskid_en to avoid tx_axis_tready from
deasserting. It must re-assert tx_axis_tvalid within 0 to 3 cycles after
tx_axis_tskid_en is deasserted.
Using tx_axis_skid_en in this aspect should prevent
tx_axis_tready from deasserting. This alleviates the need for next-cycle
response to tx_axis_tready typically required by the AXI4-Stream
tx_axis_tready/tx_axis_tvalid handshake.