Transceiver Signaling

To minimize consumption of routing resources, the various clock and data signals take on different functions depending on the configured MRMAC operating mode. The following table details the meaning of the various clock and data signals for the given MRMAC configuration settings. For FEC only modes, data/clocks are shared with the transceiver interface.

Table 1. Transceiver Signaling
MRMAC Configuration	Active MRMAC Port	Number of Active GT Lanes	Active GT Clocks	Active GT Interface Data Bus
10/25GE Narrow SerDes	0	1	rx_serdes_clk[0]	rx_serdes_data0[39:0]
	0	1	tx_core_clk[0]	tx_serdes_data0[39:0]
	1	1	rx_serdes_clk[1]	rx_serdes_data1[39:0]
	1	1	tx_core_clk[1]	tx_serdes_data1[39:0]
	2	1	rx_serdes_clk[2]	rx_serdes_data2[39:0]
	2	1	tx_core_clk[2]	tx_serdes_data2[39:0]
	3	1	rx_serdes_clk[3]	rx_serdes_data3[39:0]
	3	1	tx_core_clk[3]	tx_serdes_data3[39:0]
10/25GE Wide SerDes	0	1	rx_serdes_clk[0] rx_alt_serdes_clk[0]	rx_serdes_data0[79:0] fec_rx_din_start_0
	0	1	tx_core_clk[0] tx_alt_serdes_clk[0]	tx_serdes_data0[79:0] fec_tx_dout_start_0
	1	1	rx_serdes_clk[1] rx_alt_serdes_clk[1]	rx_serdes_data1[79:0] fec_rx_din_start_1
	1	1	tx_core_clk[1] tx_alt_serdes_clk[1]	tx_serdes_data1[79:0] fec_tx_dout_start_1
	2	1	rx_serdes_clk[2] rx_alt_serdes_clk[2]	rx_serdes_data2[79:0] fec_rx_din_start_2
	2	1	tx_core_clk[2] tx_alt_serdes_clk[2]	tx_serdes_data2[79:0] fec_tx_dout_start_2
	3	1	rx_serdes_clk[3] rx_alt_serdes_clk[3]	rx_serdes_data3[79:0] fec_rx_din_start_3
	3	1	tx_core_clk[3] tx_alt_serdes_clk[3]	tx_serdes_data3[79:0] fec_tx_dout_start_3
40GE Narrow SerDes	0	4	rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3]	rx_serdes_data0[15:0] rx_serdes_data1[15:0] rx_serdes_data2[15:0] rx_serdes_data3[15:0]
40GE Narrow SerDes	0	4	tx_core_clk[0]	tx_serdes_data0[15:0] tx_serdes_data1[15:0] tx_serdes_data2[15:0] tx_serdes_data3[15:0]
40GE Wide SerDes	0	4	rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3] rx_alt_serdes_clk[0] rx_alt_serdes_clk[1] rx_alt_serdes_clk[2] rx_alt_serdes_clk[3]	rx_serdes_data0[32:0] rx_serdes_data1[32:0] rx_serdes_data2[32:0] rx_serdes_data3[32:0]
40GE Wide SerDes	0	4	tx_core_clk[0] tx_alt_serdes_clk[0] tx_alt_serdes_clk[1] tx_alt_serdes_clk[2]	tx_serdes_data0[32:0] tx_serdes_data1[32:0] tx_serdes_data2[32:0] tx_serdes_data3[32:0]
50GE Narrow SerDes	0	1	rx_serdes_clk[0]	rx_serdes_data0[39:0]
		1	tx_core_clk[0]	tx_serdes_data0[39:0]
		2	rx_serdes_clk[1]	rx_serdes_data1[39:0]
		2	N/A	tx_serdes_data1[39:0]
	2	1	rx_serdes_clk[2]	rx_serdes_data2[39:0]
		1	tx_core_clk[2]	tx_serdes_data2[39:0]
		2	rx_serdes_clk[3]	rx_serdes_data3[39:0]
		2	N/A	tx_serdes_data3[39:0]
50GE Wide SerDes	0	2	rx_serdes_clk[0] rx_alt_serdes_clk[0]	rx_serdes_data0[79:0] fec_rx_din_start_0
	0	2	tx_core_clk[0] tx_alt_serdes_clk[0]	tx_serdes_data0[79:0] fec_tx_dout_start_0
	2	2	rx_serdes_clk[2] rx_alt_serdes_clk[2]	rx_serdes_data2[79:0] fec_rx_din_start_2
	2	2	tx_core_clk[2] tx_alt_serdes_clk[2]	tx_serdes_data2[79:0] fec_tx_dout_start_2
100GE Narrow SerDes	0	4	rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3]	rx_serdes_data0[39:0] rx_serdes_data1[39:0] rx_serdes_data2[39:0] rx_serdes_data3[39:0]
100GE Narrow SerDes	0	4	tx_core_clk[0]	tx_serdes_data0[39:0] tx_serdes_data1[39:0] tx_serdes_data2[39:0] tx_serdes_data3[39:0]
100GE Wide SerDes	0	4	rx_serdes_clk[0] rx_serdes_clk[1] rx_serdes_clk[2] rx_serdes_clk[3]	rx_serdes_data0[79:0] rx_serdes_data1[79:0] rx_serdes_data2[79:0] rx_serdes_data3[79:0]
100GE Wide SerDes	0	4	tx_core_clk[0] tx_alt_serdes_clk[0]	tx_serdes_data0[79:0] tx_serdes_data1[79:0] tx_serdes_data2[79:0] tx_serdes_data3[79:0]
The `fec_tx_dout_start` and `fec_rx_din_start` are only used in the FEC only modes and clocked by `alt_serdes_clk`.

Important: The design must meet the following rules when connecting the Versal MRMAC Hard IP core to the transceivers:

GTs have to be contiguous.
For MRMAC operating in wide SerDes mode (CTL_SERDES_WIDTH_[0..3]<2> == 1), the MRMAC and connected GTYE5_QUAD instance should be placed within the same Clock Region.
For MRMAC operating in narrow SerDes mode (CTL_SERDES_WIDTH_[0..3]<2> == 0), the MRMAC and connected GTYE5_QUAD instance should be placed either within the same Clock Region, or one horizontal Clock Regions above or below the MRMAC instance.
MRMAC 100GE, 40GE mode should use four contiguous GTYs and 50GE should use two contiguous GTYs from the same GTYE5_QUAD.

Note: MRMAC and GTYE5_QUAD placed in horizontally opposite locations are not recommended. However for extreme cases, you can try to use them by adding pipeline registers between MRMAC an GTY to ease the timing.

Transceiver Signaling - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)