The following table lists the clocks that are present in the MRMAC. Note that all datapath-related clocks are per-port. Although in certain operating modes, clocks are tied together internally and the lower-numbered port clock is used.
| Clock | Port | Description |
|---|---|---|
| AXI4-Lite | s_axi_clk | AXI4-Lite processor interface clock. |
| AXI | tx_axi_clk[2:0] rx_axi_clk[2:0] |
AXI4-Stream interface clocks. These clocks are used by the AXI4-Stream interface when in independent clock mode. They are also used by certain timestamping signals as well as a number of device statistics and flow control signals. The clocks are shared between two ports of the MRMAC. The tx_axi_clk[0] and rx_axi_clk[0] are shared between Ports 0 and 1, The tx_axi_clk[2] and rx_axi_clk[2] are shared between Ports 2 and 3. |
| core | tx_core_clk[3:0] rx_core_clk[3:0] |
Per-port high-speed clocks which drive the MRMAC internals. |
| serdes | tx_serdes_clk[3:0] rx_serdes_clk[3:0] |
Per-port high-speed clocks for the GT interface. |
| Ts | tx_ts_clk[3:0] rx_ts_clk[3:0] |
Per-port clocks for the timestamp interface. |
| Flexif | tx_flexif_clk[3:0] rx_flexif_clk[3:0] |
Per-port Flex I/F clocks. |
| alt_serdes | tx_alt_serdes_clk[3:0] rx_alt_serdes_clk[3:0] |
Per-port Alternate low-frequency clock for the GT interface. |