Xilinx IP - GT Quad Integration - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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1.3 English

Xilinx® GT based IPs like Aurora, PCIe, and MRMAC provides Block Automation in the IP integrator to enable you to connect Xilinx parent IPs to GT Quad seamlessly. IP Block Automation instantiates GT Quads and creates essential datapath, USRCLK and GT REFCLK connections.

Perform the following steps to connect MRMAC IPs using Block Automation:

  1. Add MRMAC IP using Add IP option in the IPI canvas.
  2. Configure MRMAC IP for number of lanes, line rates and so on.
  3. Click Run_Block_Automation. In the Block Automation GUI, select one of the options Auto, Start_with_New_Quad, or Customized_Connections.
  4. Perform steps 2 and 3 to add more MRMAC IP instances based on your system need.
GT Quad parameters are propagated from its connected IPs when the design is validated. Hence all GT Quad parameters are marked Auto in the Transceiver Wizard GUI. However, you can change the Auto option to Manual for Transceiver Configurations as shown in the following figure to fine tune parameters like insertion loss, drive strength, equalization, and other advanced settings. After toggling to Manual mode, any changes to the parent IP configurations followed by validation no longer propagate GT Quad parameters from parent IP to GT Quad. Manual changes should only be performed after all essential parent IP parameters are propagated to GT Quad.
Figure 1. Auto to Manual Options Switch in Transceiver Wizard