The Warp Processor is compliant with the AXI4-Lite interconnect and memory mapped AXI4
interface standards. For additional information, see the Video IP: AXI Feature Adoption
section of
Vivado Design Suite: AXI Reference
Guide (UG1037).
Note: For information on
getting video streams into and out of memory, as well as correct memory formatting, see
Video Frame Buffer Read and Video Frame Buffer Write
LogiCORE IP Product Guide (PG278).