Perform the following steps to get the .elf file from the Vitis™ Software Platform.
- Open the Vitis software
platform.
- Open the Vitis software
platform.2. Go to .
- Add the .xsa file, created using Vivado tools.
- Select XSA from
Create a New platform from the
hardware window in New Application project.
- In the New Application
Project window, select the appropriate
CPU,
OS, and
Language to
generate the application (in C language), as shown in the following figure.
- Select Empty
Application from New
Application Project window, as shown in the following
figure.
- After selecting all the options, the following window
appears.
- To create/run the design-related application .elf file, open the Explorer window in the Vitis software platform and select project name
and the appropriate application, as shown in the following figure.
- Select the target application and click OK. The following window appears.
Note: Go to "C/C++ Build settings" > "ARM v8 gcc linker">"Libraries" and add m. - Upon selecting the application source files, the Vitis software platform compiles the application
and generates an elf file in Debug folder in the Explorer window.
- Launch Vitis.
- Set workspace to v_warp_example.sdk folder in prompted window. The Vitis project opens automatically (if a welcome page shows up, close that page).
- Download the bitstream into the FPGA by selecting Xilinx Tools and then Program FPGA. The Program FPGA dialog box opens.
- Ensure that the Bitstream field shows the bitstream file
generated by Tcl script, and then click Program.Note: The DONE LED on the board turns green if the programming is successful.
- A terminal program (HyperTerminal or PuTTY) is needed for UART communication. Open the program, choose appropriate port, set baud rate to 115200, and establish Serial port connection.
- Select and right-click the application v_warp_example_design in the Project_Explorer panel.
- Select (GDB).
- Select Binaries and Qualifier in window and click OK.