| LogiCORE IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 | UltraScale+™ , UltraScale™ , 7 series FPGAs, Zynq®-7000 SoC |
| Supported User Interfaces | AXI Master Lite, AXI4-Lite |
| Resources |
Performance and Resource Use web page for Warp Filter IP Performance and Resource Use web page for Warp Initializer IP |
| Provided with Core | |
| Design Files | Not Provided |
| Example Design | Verilog |
| Test Bench | Not Provided |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Encrypted RTL |
| Supported S/W Driver 2 |
Standalone |
| Tested Design Flows 3 | |
| Design Entry | Vivado® Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 76221 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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