The Warp Initializer and Warp Filter have specific registers that allow you to control the operation of the core. All registers have an initial value of 0.
The following table provides a detailed description of all the registers that apply globally to the IP.
| Address (hex) BASEADDR+ | Register Name | Access Type | Register Description |
|---|---|---|---|
| 0x0000 | Control Signals | R/W | Bit[0] = ap_start |
| Bit[1] = ap_done | |||
| Bit[2] = ap_idle | |||
| Bit[3] = ap_ready | |||
| Bit[7] = auto_restart | |||
| Others = Reserved | |||
| 0x00004 | Global Interrupt Enable | R/W | Bit[0] = Global interrupt enable |
| Others = Reserved | |||
| 0x00008 | IP Interrupt Enable | R/W | Bit[0] = ap_done |
| Bit[1] = ap_ready | |||
| Others = reserved | |||
| 0x0000C | IP Interrupt Status Register | R/TOW (1) | Bit[0] = ap_done |
| Bit[1] = ap_ready | |||
| Others = Reserved | |||
| 0x00018 | Valid Segs Register 0 | R/W | Bit[31] to Bit[0] = Number of Valid Blocks |
| 0x00020 | Left Block Count Register | R/W | Bit[31] to Bit[0] = Number of Valid Blocks processed by the Warp Filter core 1. |
| 0x00028 | Line Number Register | R/W | Bit[31] to Bit[0] = Line Number from where Warp Filter core 2 has to read the input source image. |
| 0x00040 | Descriptor Address Register 0 | R/W | Bit[31] to Bit[0] = LSB 32 bits of the descriptor address |
| 0x00044 | Descriptor Address Register 1 | R/W | Bit[31] to Bit[0] = MSB 32 bits of the descriptor address |
Registers Description
- Control (0x00000) Register
- This register controls the operation of the Warp Initializer. Bit[0] of the Control register, ap_start, kicks off the core from software. Writing 1 to this bit starts the core. To set the core in a free running mode, Bit[7] of this register, auto_restart, must be set to 1. Bits[3:1] are not used now but reserved for future use.
- Global Interrupt Enable (0x00004) Register
- This register is the master control for all interrupts. Bit[0] can be used to enable or disable all core interrupts.
- IP Interrupt Enable (0x00008) Register
- This register allows to selectively enable interrupts. Currently, two interrupt sources are available: ap_done and ap_ready. ap_done is triggered after the frame processing is complete, and ap_ready is triggered after the core is ready to start processing the next frame.
- IP Interrupt Status (0x0000C) Register
- This is a dual purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In the readback mode (Get status), the interrupting source can be determined. In the writeback mode (Clear interrupt), the requested interrupt source bit is cleared.
- IP Descriptor Address Register 0 (0x00010) Register
- This register allows to configure the LSB 32-bit of the 64-bit descriptor address to the IP.
- IP Descriptor Address Register 0 (0x00014) Register
- This register allows to configure the MSB 32-bit of the 64-bit descriptor address to the IP.