Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

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1.0 English

This application note focuses on the design of a Digital Down-Converter (DDC) chain using AI Engine technology in Xilinx® Versal™ AI Core devices. The AI Engine is designed for high-density multiply-and-accumulate (MAC) computation that is typically seen in high-performance signal processing applications. The DDC chain is responsible for the extraction of carriers from a composite signal at a high sample rate, which requires intense computation as well as high flexibility to support various carrier configurations. This application note shows an innovative method of mapping the DDC functions to the AI Engine array by leveraging the unique architecture of Versal devices to deliver high performance and efficiency with a small memory footprint. The design methodology illustrated by this application note is applicable to a wide range of use cases including but not limited to wireless signal processing.

Download the reference design files for this application note from the Xilinx website. For detailed information about the design files, see Reference Design.