Reference Design

Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

Document ID
Release Date
1.0 English

Download the reference design files for this application note from the Xilinx® website.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter Description
Developer name Xilinx
Target devices Versal ACAP
Source code provided? Yes
Source code format (if provided) MATLAB script, AI Engine C code, and Makefile script
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. No
Functional simulation performed Yes
Timing simulation performed? No
Test bench provided for functional and timing simulation? No
Test bench format C code
Simulator software and version AI Engine Simulator in Vitis 2020.2
SPICE/IBIS simulations No
Hardware Verification
Hardware verified? Yes
Platform used for verification VCK190