Kernel And Memory Constraints

Digital Down-conversion Chain Implementation on AI Engine (XAPP1351)

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To build a scalable and compact design, it is a good practice to place the kernels, buffers, and windows carefully within a set of AI Engine tiles. The following figure shows a possible placement of two AI Engine tiles for the DDC of one antenna.

Figure 1. Two AI Engine Tiles

32 such tile pairs can be stacked in the AI Engine array of eight columns by eight rows to support 32 antennas. As shown in the following figure, each column has four input and four output 32-bit wide AXI4 streams.

Figure 2. AI Engine Array of 8x8=64 AI Engine Tiles